CIMFlow统一框架，助力数字存内计算加速器系统化设计与评估。
CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures
- 构建软硬件协同的编译与仿真流程，支持灵活指令集架构。
- 通过先进分块与并行策略，突破数字存内计算的容量限制。
- 适合从事存内计算架构研究与DNN加速器设计的开发者使用。
数字存内计算（Digital Compute-in-Memory, CIM）架构在深度神经网络（DNN）加速中展现出巨大潜力，有效缓解了“内存墙”瓶颈。然而，数字CIM加速器的开发与优化受限于缺乏涵盖软硬件设计空间的综合性工具。现有框架通常无法支持数字CIM固有的容量约束。本文提出CIMFlow，一个集成框架，提供开箱即用的DNN工作负载在数字CIM架构上的实现与评估流程。CIMFlow通过灵活的指令集架构设计，连接编译与仿真基础设施，并在编译流程中采用先进的分块与并行策略，解决数字CIM的容量限制问题。评估表明，CIMFlow可在多种配置下实现数字CIM架构的系统化原型设计与优化，为研究人员和设计者提供可扩展的设计空间探索平台。
原文摘要 · Abstract (English)
Digital Compute-in-Memory (CIM) architectures have shown great promise in Deep Neural Network (DNN) acceleration by effectively addressing the "memory wall" bottleneck. However, the development and optimization of digital CIM accelerators are hindered by the lack of comprehensive tools that encompass both software and hardware design spaces. Moreover, existing design and evaluation frameworks often lack support for the capacity constraints inherent in digital CIM architectures. In this paper, we present CIMFlow, an integrated framework that provides an out-of-the-box workflow for implementing and evaluating DNN workloads on digital CIM architectures. CIMFlow bridges the compilation and simulation infrastructures with a flexible instruction set architecture (ISA) design, and addresses the constraints of digital CIM through advanced partitioning and parallelism strategies in the compilation flow. Our evaluation demonstrates that CIMFlow enables systematic prototyping and optimization of digital CIM architectures across diverse configurations, providing researchers and designers with an accessible platform for extensive design space exploration.
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