arXiv:2505.02181cs.LGcs.AR2025-05被引 2

用时间域方法加速低复杂度机器学习中的计数运算,提升性能并降低功耗。

Efficient FPGA Implementation of Time-Domain Popcount for Low-Complexity Machine Learning

  • 通过可编程延迟线和仲裁器实现时间域计数,避免传统加法器结构。
  • 在异步Tsetlin机中实现38%延迟降低、43.1%动态功耗减少。
  • 适合资源受限场景下的高效硬件部署,尤其适用于边缘计算与低功耗设备。

人口计数(popcount)是许多低复杂度机器学习算法的关键操作,包括前景广阔的分类模型Tsetlin Machine(TM)。TM的推理机制基于每类的命题逻辑结构,再通过多数投票决定分类结果,其中投票者为布尔子句的输出。投票过程包含两个步骤:每类的popcount及通过argmax确定得票最高类。尽管TM具有轻量化优势,但其性能常受高计算开销的popcount与argmax比较限制。本文提出一种创新的时间域实现方法,利用可编程延迟线(PDL)与仲裁器,通过延迟机制高效完成上述操作。同时,我们设计了面向FPGA的实现流程,解决延迟偏差问题,确保行为符合预期功能。得益于该方法与异步架构的天然兼容性,在异步TM中实现了高达38%的延迟降低、43.1%的动态功耗减少以及15%的资源利用率提升,相比采用加法器结构的同步TM显著优化。

原文摘要 · Abstract (English)

Population count (popcount) is a crucial operation for many low-complexity machine learning (ML) algorithms, including Tsetlin Machine (TM)-a promising new ML method, particularly well-suited for solving classification tasks. The inference mechanism in TM consists of propositional logic-based structures within each class, followed by a majority voting scheme, which makes the classification decision. In TM, the voters are the outputs of Boolean clauses. The voting mechanism comprises two operations: popcount for each class and determining the class with the maximum vote by means of an argmax operation. While TMs offer a lightweight ML alternative, their performance is often limited by the high computational cost of popcount and comparison required to produce the argmax result. In this paper, we propose an innovative approach to accelerate and optimize these operations by performing them in the time domain. Our time-domain implementation uses programmable delay lines (PDLs) and arbiters to efficiently manage these tasks through delay-based mechanisms. We also present an FPGA design flow for practical implementation of the time-domain popcount, addressing delay skew and ensuring that the behavior matches that of the model's intended functionality. By leveraging the natural compatibility of the proposed popcount with asynchronous architectures, we demonstrate significant improvements in an asynchronous TM, including up to 38% reduction in latency, 43.1% reduction in dynamic power, and 15% savings in resource utilization, compared to synchronous TMs using adder-based popcount.

FPGA低功耗机器学习硬件时间域计算

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