7nm芯片上对比三类神经元电路，实现超低功耗与超高频响应。
Ultra-Low-Power Spiking Neurons in 7 nm FinFET Technology: A Comparative Analysis of Leaky Integrate-and-Fire, Morris-Lecar, and Axon-Hillock Architectures
- 在7nm FinFET中实现三类脉冲神经元电路的对比设计。
- 轴突始段结构达3GHz频响，单脉冲能耗低至阿焦耳级。
- 适合超低功耗智能硬件与高算力神经形态芯片研发者。
类脑计算旨在为大规模人工智能应用复制大脑的能效优势与并行处理能力。本文在7 nm FinFET工艺中对三类脉冲神经元电路——漏电积分发放（LIF）、Morris-Lecar（ML）和轴突始段（AH）架构进行了全面比较研究。通过大量SPICE仿真，系统优化了脉冲频率、每脉冲能耗及静态功耗。结果表明，AH设计实现最高吞吐量，支持高达3 GHz的多吉赫兹脉冲频率，单脉冲能耗低至阿焦耳量级。相比之下，ML架构在亚阈值至近阈值区表现优异，实现最低0.385 aJ/spike的低功耗运行，并具备生物性爆发放电特性。尽管LIF因采用解耦电流镜可实现高频操作，但在高供电电压下静态泄漏略高于ML与AH。与22 nm平面、28 nm工艺对比显示，7 nm FinFET显著提升能效与速度，但深亚阈值区域子阈值泄漏增加。本研究量化各类架构的设计权衡，为先进纳米尺度下脉冲神经元电路优化提供路线图，助力实现兼具超低功耗与高计算吞吐的类脑硬件。
原文摘要 · Abstract (English)
Neuromorphic computing aims to replicate the brain's remarkable energy efficiency and parallel processing capabilities for large-scale artificial intelligence applications. In this work, we present a comprehensive comparative study of three spiking neuron circuit architectures-Leaky-Integrate-and-Fire (LIF), Morris-Lecar (ML), and Axon-Hillock (AH)-implemented in a 7 nm FinFET technology. Through extensive SPICE simulations, we explore the optimization of spiking frequency, energy per spike, and static power consumption. Our results show that the AH design achieves the highest throughput, demonstrating multi-gigahertz firing rates (up to 3 GHz) with attojoule energy costs. By contrast, the ML architecture excels in subthreshold to near-threshold regimes, offering robust low-power operation (as low as 0.385 aJ/spike) and biological bursting behavior. Although LIF benefits from a decoupled current mirror for high-frequency operation, it exhibits slightly higher static leakage compared to ML and AH at elevated supply voltages. Comparisons with previous node implementations (22 nm planar, 28 nm) reveal that 7 nm FinFETs can drastically boost energy efficiency and speed albeit at the cost of increased subthreshold leakage in deep subthreshold regions. By quantifying design trade-offs for each neuron architecture, our work provides a roadmap for optimizing spiking neuron circuits in advanced nanoscale technologies to deliver neuromorphic hardware capable of both ultra-low-power operation and high computational throughput.
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