用开源数据集训练出无版权风险的硬件代码生成模型
Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs
- 构建22万+文件的免费开源Verilog数据集，自动筛选确保合法使用
- 训练出的FreeV模型版权侵权率仅3%，功能评测提升超10%
- 适合需要安全生成硬件代码的研究者和工业界开发者
大型语言模型在生成功能性Verilog代码方面存在能力局限，现有方法依赖开源仓库中的定制化硬件数据集进行微调，但这些数据集规模有限且缺乏版权审查，可能导致模型生成受版权保护的代码。为此，我们提出一个评估基准，用于衡量训练后模型生成受版权保护代码的风险。为降低该风险，我们发布了一个包含超过22万份文件的开源Verilog数据集FreeSet，以及用于保障公平使用的自动化数据清洗框架。在此基础上，我们采用持续预训练的微调框架，训练出针对Verilog的Llama模型FreeV。实验表明，FreeV在同类工作中具有最低的版权侵权风险，违规率仅为3%；同时在功能生成性能上优于基线模型，VerilogEval pass@10指标提升超过10%。
原文摘要 · Abstract (English)
Limitations in Large Language Model (LLM) capabilities for hardware design tasks, such as generating functional Verilog codes, have motivated various fine-tuning optimizations utilizing curated hardware datasets from open-source repositories. However, these datasets remain limited in size and contain minimal checks on licensing for reuse, resulting in potential copyright violations by fine-tuned LLMs. Therefore, we propose an evaluation benchmark to estimate the risk of Verilog-trained LLMs to generate copyright-protected codes. To minimize this risk, we present an open-source Verilog dataset, FreeSet, containing over 220k files, along with the automated dataset curation framework utilized to provide additional guarantees of fair-use Verilog data. We then execute an LLM fine-tuning framework consisting of continual pre-training, resulting in a fine-tuned Llama model for Verilog, FreeV. Our results indicate that FreeV demonstrates the smallest risk of copyright-infringement among prior works, with only a 3% violation rate. Furthermore, experimental results demonstrate improvements in Verilog generation functionality over its baseline model, improving VerilogEval pass@10 rates by over 10%.
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