用开关电容电路实现高效内存计算的门控循环单元。
MINIMALIST: switched-capacitor circuits for efficient in-memory computation of gated recurrent units
- 用开关电容电路实现内存内计算与门控更新
- 在时间序列数据上验证了硬件兼容性，性能接近纯软件模型
- 仅用通用电路元件，利于跨工艺节点扩展
循环神经网络（RNN）长期被视为处理时序数据的理想选择，尤其适用于嵌入式边缘计算中资源受限的系统。近期训练范式的进步催生了新一代高效的RNN。本文提出一种简化的最小化门控循环单元（GRU）架构及其配套的混合信号硬件实现。该设计利用开关电容电路不仅实现内存内计算（IMC），还用于门控状态更新。混合信号核心仅依赖金属电容、传输门和时钟比较器等通用电路，极大促进其向其他工艺节点的可扩展性与迁移。我们在时间序列数据上对架构性能进行了基准测试，并引入了直接映射至硬件系统的全部约束条件。混合信号仿真验证了直接兼容性，复现了纯软件模型记录的数据。
原文摘要 · Abstract (English)
Recurrent neural networks (RNNs) have been a long-standing candidate for processing of temporal sequence data, especially in memory-constrained systems that one may find in embedded edge computing environments. Recent advances in training paradigms have now inspired new generations of efficient RNNs. We introduce a streamlined and hardware-compatible architecture based on minimal gated recurrent units (GRUs), and an accompanying efficient mixed-signal hardware implementation of the model. The proposed design leverages switched-capacitor circuits not only for in-memory computation (IMC), but also for the gated state updates. The mixed-signal cores rely solely on commodity circuits consisting of metal capacitors, transmission gates, and a clocked comparator, thus greatly facilitating scaling and transfer to other technology nodes. We benchmark the performance of our architecture on time series data, introducing all constraints required for a direct mapping to the hardware system. The direct compatibility is verified in mixed-signal simulations, reproducing data recorded from the software-only network model.
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