用精准指令模拟器加速机器学习自动调优，省硬件、提效率。
Introducing Instruction-Accurate Simulators for Performance Estimation of Autotuning Workloads
- 用指令级精确模拟器替代真实硬件执行调优任务
- 预测准确率高，最优实现始终在前3%内
- 仅需3个并行模拟器即可超越部分嵌入式硬件原生性能
加速机器学习工作负载需要高效方法，因其优化空间庞大。自动调优已成为系统评估实现变体的有效手段。传统方式需在目标硬件上运行工作负载。本文提出一种接口，支持在模拟器上执行自动调优任务。该方法在目标硬件不可用时具备高可扩展性，可在任意可用硬件上并行运行大量模拟。我们评估了使用快速指令准确模拟器进行自动调优的可行性，训练多种预测器，基于模拟统计量预测工作负载在目标硬件上的性能。结果表明，调优后的预测器表现优异：在测试的x86、ARM和RISC-V架构上，实际运行时间最优的实现始终位于预测结果的前3%。在最佳情况下，仅需在三个模拟器上并行运行三个样本，其性能即超越嵌入式架构的原生执行。
原文摘要 · Abstract (English)
Accelerating Machine Learning (ML) workloads requires efficient methods due to their large optimization space. Autotuning has emerged as an effective approach for systematically evaluating variations of implementations. Traditionally, autotuning requires the workloads to be executed on the target hardware (HW). We present an interface that allows executing autotuning workloads on simulators. This approach offers high scalability when the availability of the target HW is limited, as many simulations can be run in parallel on any accessible HW. Additionally, we evaluate the feasibility of using fast instruction-accurate simulators for autotuning. We train various predictors to forecast the performance of ML workload implementations on the target HW based on simulation statistics. Our results demonstrate that the tuned predictors are highly effective. The best workload implementation in terms of actual run time on the target HW is always within the top 3 % of predictions for the tested x86, ARM, and RISC-V-based architectures. In the best case, this approach outperforms native execution on the target HW for embedded architectures when running as few as three samples on three simulators in parallel.
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