针对FPGA部署卷积神经网络，提出算术优化综合方案
An Overview of Arithmetic Adaptations for Inference of Convolutional Neural Networks on Re-configurable Hardware
- 融合批归一化、滤波器剪枝与量化训练提升推理效率
- 在XILINX Artix-7 FPGA上实现TinyYOLOv3高效部署
- 适合嵌入式视觉系统开发人员参考部署优化策略
卷积神经网络（CNN）在计算机视觉任务中广泛应用，但其在可重构硬件如现场可编程门阵列（FPGA）上的部署面临计算强度高、内存需求大和算术条件严苛等挑战。为此，本文提出针对小型目标检测器TinyYOLOv3在XILINX Artix-7 FPGA上的优化方法，采用批归一化融合、滤波器剪枝和训练后量化等技术，显著降低资源占用并提升推理速度，验证了在嵌入式平台高效部署CNN的可行性。
原文摘要 · Abstract (English)
Convolutional Neural Networks (CNNs) have gained high popularity as a tool for computer vision tasks and for that reason are used in various applications. There are many different concepts, like single shot detectors, that have been published for detecting objects in images or video streams. However, CNNs suffer from disadvantages regarding the deployment on embedded platforms such as re-configurable hardware like Field Programmable Gate Arrays (FPGAs). Due to the high computational intensity, memory requirements and arithmetic conditions, a variety of strategies for running CNNs on FPGAs have been developed. The following methods showcase our best practice approaches for a TinyYOLOv3 detector network on a XILINX Artix-7 FPGA using techniques like fusion of batch normalization, filter pruning and post training network quantization.
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