为RISC-V处理器设计轻量可扩展的浮点运算方案，兼顾精度与兼容性。
Enable Lightweight and Precision-Scalable Posit/IEEE-754 Arithmetic in RISC-V Cores for Transprecision Computing
- 在原有浮点单元中集成专用正数编码器，实现轻量化部署。
- 支持动态指数位宽，可在不同精度间灵活切换，提升计算效率。
- 兼容IEEE-754标准，适合需要高精度与低功耗的嵌入式场景。
尽管正数格式在可变精度计算中具有更优的动态范围和精度，但其在RISC-V处理器中的应用受限于缺乏轻量、可扩展且兼容IEEE-754标准的硬件实现方案。为此，本文通过三项改进：1）在原始浮点单元中集成专用正数编解码器，实现轻量化设计；2）引入多/混合精度支持及动态指数位宽机制，实现精度可扩展；3）复用并定制指令集扩展，确保正数操作与IEEE-754兼容。综合评估涵盖修改后的浮点单元、RISC-V核心及SoC层级。结果表明，相比现有最优正数增强型RISC-V处理器，本方案在逻辑门（LUTs）上减少47.9%，触发器（FFs）减少57.4%，并在多种GEMM核上实现最高达2.54倍的吞吐量提升。
原文摘要 · Abstract (English)
While posit format offers superior dynamic range and accuracy for transprecision computing, its adoption in RISC-V processors is hindered by the lack of a unified solution for lightweight, precision-scalable, and IEEE-754 arithmetic compatible hardware implementation. To address these challenges, we enhance RISC-V processors by 1) integrating dedicated posit codecs into the original FPU for lightweight implementation, 2) incorporating multi/mixed-precision support with dynamic exponent size for precision-scalability, and 3) reusing and customizing ISA extensions for IEEE-754 compatible posit operations. Our comprehensive evaluation spans the modified FPU, RISC-V core, and SoC levels. It demonstrates that our implementation achieves 47.9% LUTs and 57.4% FFs reduction compared to state-of-the-art posit-enabled RISC-V processors, while achieving up to 2.54$\times$ throughput improvement in various GEMM kernels.
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