用大模型自动生成更高效的Chisel硬件代码，还能自我纠错优化。
ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
- 通过编译仿真反馈循环改进生成代码，实现自我修正。
- 在生成成功率上达到当前顶尖水平，接近Verilog系统表现。
- 适合想快速开发可维护硬件设计的工程师和研究者。
使用硬件描述语言（HDL）如Verilog编写代码耗时费力。随着大语言模型（LLMs）的快速发展，利用LLMs辅助编写HDL代码成为热门方向。已有工作证明了LLM将自然语言转化为传统Verilog的潜力。Chisel是一种基于Scala的下一代HDL，提供更高层次抽象，使硬件设计更简洁、易维护且可扩展。然而，利用LLM生成Chisel代码的潜力尚未被充分探索。本文提出ReChisel，一种基于LLM的智能体系统，旨在提升Chisel代码生成的有效性。ReChisel引入反思机制，通过编译与仿真反馈迭代优化生成代码质量，并设置逃生机制避免陷入无进展循环。实验表明，ReChisel显著提升了Chisel代码生成的成功率，性能达到当前最先进的基于LLM的智能体系统在Verilog生成中的水平。
原文摘要 · Abstract (English)
Coding with hardware description languages (HDLs) such as Verilog is a time-intensive and laborious task. With the rapid advancement of large language models (LLMs), there is increasing interest in applying LLMs to assist with HDL coding. Recent efforts have demonstrated the potential of LLMs in translating natural language to traditional HDL Verilog. Chisel, a next-generation HDL based on Scala, introduces higher-level abstractions, facilitating more concise, maintainable, and scalable hardware designs. However, the potential of using LLMs for Chisel code generation remains largely unexplored. This work proposes ReChisel, an LLM-based agentic system designed to enhance the effectiveness of Chisel code generation. ReChisel incorporates a reflection mechanism to iteratively refine the quality of generated code using feedback from compilation and simulation processes, and introduces an escape mechanism to break free from non-progress loops. Experiments demonstrate that ReChisel significantly improves the success rate of Chisel code generation, achieving performance comparable to state-of-the-art LLM-based agentic systems for Verilog code generation.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。