用强化学习提升大模型生成符合约束的模拟电路拓扑。
AUTOCIRCUIT-RL: Reinforcement Learning-Driven LLM for Automated Circuit Topology Generation
- 大模型先学指令生成，再通过奖励模型优化设计质量。
- 有效电路生成率提升12%，效率提高14%，重复率降低38%。
- 适合芯片设计自动化领域，尤其擅长少样本复杂电路生成。
模拟电路拓扑合成是电子设计自动化（EDA）的核心环节，可自动生成满足特定需求的电路结构。然而，庞大的设计空间与严格的约束条件使高效合成极具挑战。本文提出AUTOCIRCUIT-RL，一种基于强化学习（RL）的新型框架，用于自动化模拟电路合成。该框架分两阶段运行：首先进行指令微调，使大语言模型（LLM）从编码设计约束的结构化提示中学习生成电路拓扑；其次通过奖励模型对有效性、效率和输出电压进行评估，进一步优化已微调的模型。最终生成的模型可直接输出满足设计约束的拓扑。实验表明，AUTOCIRCUIT-RL相比最优基线，有效电路生成率提升约12%，效率提升约14%，重复生成率降低约38%。在有限训练数据下，成功合成有效电路的比例超过60%，展现出强泛化能力。结果表明，该框架在保持高效性和约束遵循性的同时，能有效拓展至复杂电路，标志着人工智能驱动电路设计的重要进展。
原文摘要 · Abstract (English)
Analog circuit topology synthesis is integral to Electronic Design Automation (EDA), enabling the automated creation of circuit structures tailored to specific design requirements. However, the vast design search space and strict constraint adherence make efficient synthesis challenging. Leveraging the versatility of Large Language Models (LLMs), we propose AUTOCIRCUIT-RL,a novel reinforcement learning (RL)-based framework for automated analog circuit synthesis. The framework operates in two phases: instruction tuning, where an LLM learns to generate circuit topologies from structured prompts encoding design constraints, and RL refinement, which further improves the instruction-tuned model using reward models that evaluate validity, efficiency, and output voltage. The refined model is then used directly to generate topologies that satisfy the design constraints. Empirical results show that AUTOCIRCUIT-RL generates ~12% more valid circuits and improves efficiency by ~14% compared to the best baselines, while reducing duplicate generation rates by ~38%. It achieves over 60% success in synthesizing valid circuits with limited training data, demonstrating strong generalization. These findings highlight the framework's effectiveness in scaling to complex circuits while maintaining efficiency and constraint adherence, marking a significant advancement in AI-driven circuit design.
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