用波形数据自动定位芯片设计错误模块，提速故障排查。
VCDiag: Classifying Erroneous Waveforms for Failure Triage Acceleration
- 基于VCD数据选信号并压缩，保留关键特征
- 大设计下定位准确率超94%，缩小排查范围
- 适配多种Verilog设计，可直接集成到测试流程
芯片设计验证中的故障排查耗时严重，依赖人工审查规格、日志和波形。尽管机器学习在激励生成和覆盖率闭合方面已有进展，但在大规模RTL级仿真故障分类上的应用仍有限。VCDiag利用VCD数据实现波形分类，精准定位潜在故障模块。在最大规模实验中，该方法对前三个最可能出错模块的识别准确率超过94%。其框架提出新颖的信号选择与统计压缩方法，使原始数据量减少120倍以上，同时保留分类所需的关键特征。该方法可无缝集成至多种Verilog/SystemVerilog设计及测试平台。
原文摘要 · Abstract (English)
Failure triage in design functional verification is critical but time-intensive, relying on manual specification reviews, log inspections, and waveform analyses. While machine learning (ML) has improved areas like stimulus generation and coverage closure, its application to RTL-level simulation failure triage, particularly for large designs, remains limited. VCDiag offers an efficient, adaptable approach using VCD data to classify failing waveforms and pinpoint likely failure locations. In the largest experiment, VCDiag achieves over 94% accuracy in identifying the top three most likely modules. The framework introduces a novel signal selection and statistical compression approach, achieving over 120x reduction in raw data size while preserving features essential for classification. It can also be integrated into diverse Verilog/SystemVerilog designs and testbenches.
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