构建首个硬件代码翻译数据集，提升大模型生成Verilog的能力
hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation
- 将VHDL、Chisel等语言代码自动转为Verilog，扩充高质量数据
- 使320亿参数模型在评测中通过率提升23%，无需额外训练技巧
- 适合硬件设计与大模型结合方向的研究者使用
大型语言模型在代码生成领域日益重要，尤其在硬件设计中，Verilog是关键语言。然而，公开可用的Verilog代码远少于Python等软件语言。本文提出hdl2v（HDL-to-Verilog）数据集，通过将VHDL、Chisel和PyMTL3三种硬件描述语言代码自动翻译或编译为Verilog，显著增加高质量人类编写Verilog数据。实验表明，该数据集可使320亿参数开源模型在VerilogEvalV2评测中通过率（pass@10）提升23%，且无需数据增强或知识蒸馏。同时，在基于数据增强的微调方法中，性能提升达63%。本文还对数据集特性进行分析，为未来优化提供方向。
原文摘要 · Abstract (English)
Large language models (LLMs) are playing an increasingly large role in domains such as code generation, including hardware code generation, where Verilog is the key language. However, the amount of publicly available Verilog code pales in comparison to the amount of code available for software languages like Python. In this work, we present hdl2v ("HDL-to-Verilog"), a dataset which seeks to increase the amount of available human-written Verilog data by translating or compiling three other hardware description languages - VHDL, Chisel, and PyMTL3 - to Verilog. Furthermore, we demonstrate the value of hdl2v in enhancing LLM Verilog generation by improving performance of a 32 billion-parameter open-weight model by up to 23% (pass@10) in VerilogEvalV2, without utilizing any data augmentation or knowledge distillation from larger models. We also show hdl2v's ability to boost the performance of a data augmentation-based fine-tuning approach by 63%. Finally, we characterize and analyze our dataset to better understand which characteristics of HDL-to-Verilog datasets can be expanded upon in future work for even better performance.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。