基于RISC-V的定制DSP加速器芯片，能效比ARM高17%。
Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing
- 采用可扩展的RISC-V架构，集成乘法与原子操作指令扩展。
- 在相似制程下，功耗比ARM Cortex-M0低17%，CPI表现优异。
- 适合边缘计算场景，开放标准便于领域定制优化。
本文系统分析了RISC-V指令集架构，聚焦其模块化设计、实现挑战与性能特征。研究基于RV32I基础指令集，扩展乘法（M）和原子操作（A）功能。通过流水线实现的周期精确仿真，评估了每条指令周期数（CPI）和能效表现。结果表明，RISC-V在嵌入式系统中具备优势，且易于集成定制加速器。对比分析显示，在相同工艺节点下，其功耗较ARM Cortex-M0降低17%。RISC-V的开源标准为特定领域优化提供了显著灵活性。
原文摘要 · Abstract (English)
This paper presents a comprehensive analysis of the RISC-V instruction set architecture, focusing on its modular design, implementation challenges, and performance characteristics. We examine the RV32I base instruction set with extensions for multiplication (M) and atomic operations (A). Through cycle-accurate simulation of a pipelined implementation, we evaluate performance metrics including CPI (cycles per instruction) and power efficiency. Our results demonstrate RISC-V's advantages in embedded systems and its scalability for custom accelerators. Comparative analysis shows a 17% reduction in power consumption compared to ARM Cortex-M0 implementations in similar process nodes. The open-standard nature of RISC-V provides significant flexibility for domain-specific optimizations.
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