用大模型分析Verilog代码，精准定位导致设计缺陷的代码行。
VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code
- 利用大模型提取Verilog代码的行级与模块级嵌入特征
- 线级时序和布线拥塞预测F1得分达0.86-0.95，误差降至4%
- 首次实现从Verilog代码直接预测代码行级设计质量，适合芯片设计优化
现代芯片设计复杂度高，亟需在早期阶段直接从Verilog代码（硬件设计常用编程语言）中预测关键设计质量指标，如时序和布线拥塞。尤其重要但困难的是定位引发时序违规或下游布线拥塞的具体代码行。已有工作尝试将Verilog转换为中间图表示，并结合LLM嵌入与其他特征进行模块级质量预测，但未涉及行级预测。本文提出VeriLoC，首个直接从Verilog代码同时实现行级与模块级质量预测的方法。VeriLoC利用最新的Verilog代码生成大模型提取局部行级与模块级嵌入，并在拼接后的嵌入上训练下游分类器/回归器。实验表明，VeriLoC在线级拥塞与时序预测上取得0.86–0.95的高F1分数，将现有方法14%–18%的平均百分比误差降至仅4%。我们认为VeriLoC的嵌入及研究洞察对复杂硬件设计的其他预测与优化任务亦具价值。
原文摘要 · Abstract (English)
Modern chip design is complex, and there is a crucial need for early-stage prediction of key design-quality metrics like timing and routing congestion directly from Verilog code (a commonly used programming language for hardware design). It is especially important yet complex to predict individual lines of code that cause timing violations or downstream routing congestion. Prior works have tried approaches like converting Verilog into an intermediate graph representation and using LLM embeddings alongside other features to predict module-level quality, but did not consider line-level quality prediction. We propose VeriLoC, the first method that predicts design quality directly from Verilog at both the line- and module-level. To this end, VeriLoC leverages recent Verilog code-generation LLMs to extract local line-level and module-level embeddings, and train downstream classifiers/regressors on concatenations of these embeddings. VeriLoC achieves high F1-scores of 0.86-0.95 for line-level congestion and timing prediction, and reduces the mean average percentage error from 14% - 18% for SOTA methods down to only 4%. We believe that VeriLoC embeddings and insights from our work will also be of value for other predictive and optimization tasks for complex hardware design.
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