用图注意力网络提升芯片设计相似性评估，加速方案复用。
Pieceformer: Similarity-Driven Knowledge Transfer via Scalable Graph Transformer in VLSI
- 设计混合消息传递与图变压器架构，支持大规模电路图相似性计算。
- 在真实电路数据上将平均误差降低24.9%，并正确聚类所有设计组。
- 适合芯片设计自动化、EDA工具开发人员参考，可显著减少布局耗时。
准确的图相似性对VLSI设计中的知识迁移至关重要，能重用已有方案以降低工程成本和缩短交付周期。我们提出Pieceformer，一种可扩展的自监督相似性评估框架，采用混合消息传递与图变压器编码器。为解决变压器扩展性问题，引入线性变压器主干，并设计分块训练流程以高效管理内存与并行计算。在合成数据与真实世界CircuitNet数据集上的评估显示，Pieceformer相较基线方法平均绝对误差（MAE）降低24.9%，是唯一能正确聚类所有真实设计组的方法。通过分区任务案例研究进一步验证，模型可实现最高89%的运行时间缩减。结果表明该框架在现代VLSI系统中具备高效、无偏的设计复用能力。
原文摘要 · Abstract (English)
Accurate graph similarity is critical for knowledge transfer in VLSI design, enabling the reuse of prior solutions to reduce engineering effort and turnaround time. We propose Pieceformer, a scalable, self-supervised similarity assessment framework, equipped with a hybrid message-passing and graph transformer encoder. To address transformer scalability, we incorporate a linear transformer backbone and introduce a partitioned training pipeline for efficient memory and parallelism management. Evaluations on synthetic and real-world CircuitNet datasets show that Pieceformer reduces mean absolute error (MAE) by 24.9% over the baseline and is the only method to correctly cluster all real-world design groups. We further demonstrate the practical usage of our model through a case study on a partitioning task, achieving up to 89% runtime reduction. These results validate the framework's effectiveness for scalable, unbiased design reuse in modern VLSI systems.
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