用递归网络优化ΔΣ型模数转换器设计，兼顾精度与面积。
RCNet: $ΔΣ$ IADCs as Recurrent AutoEncoders
- 将RNN用于建模ΔΣ调制器与滤波器，类比增量式ADC结构
- 在80倍过采样下实现13位以上信噪比，电容总面积小于14pF
- 无需高阶调制器，通过拓扑探索获得更优硬件设计
本文提出一种针对ΔΣ模数转换器（ADC）的深度学习模型RCNet。利用循环神经网络（RNN）建模调制器与滤波器，该方法被拓展至增量式ADC（IADC）。结合高端优化器与全定制损失函数，引入量化权重、信号饱和、时序噪声注入及器件面积等硬件约束。聚焦直流转换任务，早期结果表明，在特定硬件映射复杂度下可优化信噪比（以有效位数ENOB衡量）。所提RCNet在给定80倍过采样率下，实现超过13位的信噪比，同时总电容面积小于14pF。有趣的是，最优架构并不依赖高阶调制器，而是利用额外的拓扑探索自由度获得性能突破。
原文摘要 · Abstract (English)
This paper proposes a deep learning model (RCNet) for Delta-Sigma ($ΔΣ$) ADCs. Recurrent Neural Networks (RNNs) allow to describe both modulators and filters. This analogy is applied to Incremental ADCs (IADC). High-end optimizers combined with full-custom losses are used to define additional hardware design constraints: quantized weights, signal saturation, temporal noise injection, devices area. Focusing on DC conversion, our early results demonstrate that $SNR$ defined as an Effective Number Of Bits (ENOB) can be optimized under a certain hardware mapping complexity. The proposed RCNet succeeded to provide design tradeoffs in terms of $SNR$ ($>$13bit) versus area constraints ($<$14pF total capacitor) at a given $OSR$ (80 samples). Interestingly, it appears that the best RCNet architectures do not necessarily rely on high-order modulators, leveraging additional topology exploration degrees of freedom.
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