用大模型实现跨架构的可验证寄存器分配，提升编译效率与性能。
VeriLocc: End-to-End Cross-Architecture Register Allocation via LLM
- 结合LLM与形式化验证，将中间表示转为目标架构寄存器分配
- 单次成功率85-99%，100次内通过率接近100%
- 比人工调优库快10%以上，适合硬件快速迭代场景
现代GPU发展迅速，但生产级编译器仍依赖人工设计的寄存器分配启发式算法，每代硬件都需大量重调。我们提出VeriLocc框架，融合大语言模型（LLMs）与形式化编译技术，实现跨架构的可泛化、可验证寄存器分配。VeriLocc微调LLM，将中间表示（MIR）映射为特定目标的寄存器分配，借助静态分析进行跨架构归一化与泛化，并通过验证器引导的再生循环确保正确性。在矩阵乘法（GEMM）和多头注意力（MHA）上评估，VeriLocc实现85-99%的单次准确率，以及接近100%的pass@100。案例研究显示，其发现的分配方案优于专家调优库，运行时间比rocBLAS快超过10%。
原文摘要 · Abstract (English)
Modern GPUs evolve rapidly, yet production compilers still rely on hand-crafted register allocation heuristics that require substantial re-tuning for each hardware generation. We introduce VeriLocc, a framework that combines large language models (LLMs) with formal compiler techniques to enable generalizable and verifiable register allocation across GPU architectures. VeriLocc fine-tunes an LLM to translate intermediate representations (MIRs) into target-specific register assignments, aided by static analysis for cross-architecture normalization and generalization and a verifier-guided regeneration loop to ensure correctness. Evaluated on matrix multiplication (GEMM) and multi-head attention (MHA), VeriLocc achieves 85-99% single-shot accuracy and near-100% pass@100. Case study shows that VeriLocc discovers more performant assignments than expert-tuned libraries, outperforming rocBLAS by over 10% in runtime.
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