用AI代理自动完成芯片设计与验证，效率超95%覆盖
Hey AI, Generate Me a Hardware Code! Agentic AI-based Hardware Design & Verification
- 构建可自主迭代的AI代理系统，结合人工干预实现端到端设计
- 在5个开源项目上达成95%以上验证覆盖率，时间显著减少
- 适合芯片设计初学者、自动化团队及快速原型开发人员
现代集成电路日益复杂，其开发过程也愈发繁琐。硬件设计验证需系统化规划、执行与确认，以确保无错误流片，但该过程耗时费力。自然语言处理领域因大语言模型（LLMs）的发展迎来变革，生成式AI（GenAI）已能高效理解与生成人类语言，在包括硬件设计验证在内的诸多应用中展现潜力。本文提出一种基于智能体（agentic AI）的硬件设计与验证方法，使AI代理在人机协同（HITL）介入下，实现动态、迭代与自我反思的全流程工作，完成从设计到验证的端到端任务。该方法在5个开源设计上进行评估，验证覆盖率超过95%，同时显著缩短验证时间，并展现出更优性能、适应性与可配置性。
原文摘要 · Abstract (English)
Modern Integrated Circuits (ICs) are becoming increasingly complex, and so is their development process. Hardware design verification entails a methodical and disciplined approach to the planning, development, execution, and sign-off of functionally correct hardware designs. This tedious process requires significant effort and time to ensure a bug-free tape-out. The field of Natural Language Processing has undergone a significant transformation with the advent of Large Language Models (LLMs). These powerful models, often referred to as Generative AI (GenAI), have revolutionized how machines understand and generate human language, enabling unprecedented advancements in a wide array of applications, including hardware design verification. This paper presents an agentic AI-based approach to hardware design verification, which empowers AI agents, in collaboration with Humain-in-the-Loop (HITL) intervention, to engage in a more dynamic, iterative, and self-reflective process, ultimately performing end-to-end hardware design and verification. This methodology is evaluated on five open-source designs, achieving over 95% coverage with reduced verification time while demonstrating superior performance, adaptability, and configurability.
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