构建40万+硬件设计数据集，推动机器学习优化硬件生成
ForgeHLS: A Large-Scale, Open-Source Dataset for High-Level Synthesis
- 从846个核函数生成40万+设计，自动添加循环展开等优化指令
- 涵盖200k CPU小时计算量，覆盖多种应用场景与优化策略
- 适合做硬件自动优化的机器学习研究者使用
高层次综合（HLS）在现代硬件设计中至关重要，能将高级代码转化为优化的硬件实现。然而，机器学习应用于HLS优化的研究受限于缺乏足够大规模和多样性的数据集。为此，我们提出ForgeHLS，一个专为机器学习驱动的HLS研究设计的大规模开源数据集。ForgeHLS包含超过40万种由846个核函数生成的多样化设计，涵盖广泛的应用领域，在构建过程中消耗超过200,000 CPU小时。每个核函数均通过系统化自动化插入调度指令（如循环展开、流水线化、数组分区），并结合贝叶斯优化进行广泛的架构空间探索。相比现有数据集，ForgeHLS在规模、多样性与设计覆盖方面均有显著提升。我们进一步定义并评估了典型的下游任务，包括质量结果（QoR）预测与自动调度指令探索，清晰展示了其在开发和改进基于机器学习的HLS优化方法中的实用性。数据集与代码已公开于https://github.com/zedong-peng/ForgeHLS。
原文摘要 · Abstract (English)
High-Level Synthesis (HLS) plays a crucial role in modern hardware design by transforming high-level code into optimized hardware implementations. However, progress in applying machine learning (ML) to HLS optimization has been hindered by a shortage of sufficiently large and diverse datasets. To bridge this gap, we introduce ForgeHLS, a large-scale, open-source dataset explicitly designed for ML-driven HLS research. ForgeHLS comprises over 400k diverse designs generated from 846 kernels covering a broad range of application domains, consuming over 200k CPU hours during dataset construction. Each kernel includes systematically automated pragma insertions (loop unrolling, pipelining, array partitioning), combined with extensive design space exploration using Bayesian optimization. Compared to existing datasets, ForgeHLS significantly enhances scale, diversity, and design coverage. We further define and evaluate representative downstream tasks in Quality of Result (QoR) prediction and automated pragma exploration, clearly demonstrating ForgeHLS utility for developing and improving ML-based HLS optimization methodologies. The dataset and code are public at https://github.com/zedong-peng/ForgeHLS.
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