用图神经网络预测芯片布线后电容，速度快929倍且更准。
Effective Capacitance Modeling Using Graph Neural Networks
- 用图神经网络建模布线后的有效电容，替代传统估算方法。
- 在真实芯片上实现929倍加速，精度优于现有启发式算法。
- 适合需要快速精准时序分析的芯片设计工程师使用。
静态时序分析是VLSI设计流程中的关键步骤，用于验证电路时序正确性。时序分析依赖于电路的布局布线结果，而布局布线效率又受最终时序性能影响。通过引入时序相关预测，可优化设计早期阶段。有效电容是门延迟计算的关键输入，精确值需依赖布线或布线估计。本文提出首个基于图神经网络的布线后有效电容建模方法GNN-Ceff，利用GPU并行化实现显著提速，同时精度优于当前启发式方法。GNN-Ceff在真实基准测试中相比串行运行的最先进方法实现929倍加速。
原文摘要 · Abstract (English)
Static timing analysis is a crucial stage in the VLSI design flow that verifies the timing correctness of circuits. Timing analysis depends on the placement and routing of the design, but at the same time, placement and routing efficiency depend on the final timing performance. VLSI design flows can benefit from timing-related prediction to better perform the earlier stages of the design flow. Effective capacitance is an essential input for gate delay calculation, and finding exact values requires routing or routing estimates. In this work, we propose the first GNN-based post-layout effective capacitance modeling method, GNN-Ceff, that achieves significant speed gains due to GPU parallelization while also providing better accuracy than current heuristics. GNN-Ceff parallelization achieves 929x speedup on real-life benchmarks over the state-of-the-art method run serially.
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