提出可配置的电压模式胜者为王电路，低功耗实现多胜者与滞回功能。
Voltage Mode Winner-Take-All Circuit for Neuromorphic Systems
- 基于电压模式设计，支持k胜者与滞回特性配置
- 处理1000个输入仅耗电34.9μW，延迟10.4ns
- 适用于神经形态系统中的空间滤波与分类任务
神经形态计算近年来展现出低功耗下的本地学习能力，其中胜者为王电路是关键组件。本文提出一种可配置的电压模式胜者为王电路，支持k胜者和滞回特性，在IBM 65 nm工艺节点上完成仿真。该电路在处理1000个输入时功耗仅为34.9 μW，延迟为10.4 ns。电路在空间滤波和分类任务中验证了其有效性。
原文摘要 · Abstract (English)
Recent advances in neuromorphic computing demonstrate on-device learning capabilities with low power consumption. One of the key learning units in these systems is the winner-take-all circuit. In this research, we propose a winner-take-all circuit that can be configured to achieve k-winner and hysteresis properties, simulated in IBM 65 nm node. The circuit dissipated 34.9 $μ$W of power with a latency of 10.4 ns, while processing 1000 inputs. The utility of the circuit is demonstrated for spatial filtering and classification.
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