提出高效分布式算法，让FPGA上神经网络更快更省资源。
da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAs
- 用分布式计算优化矩阵乘法，降低FPGA资源占用。
- 实测可减少三分之一片上资源，同时降低延迟。
- 适合高实时性场景，如粒子物理探测器中的神经网络部署。
在大型强子对撞机（CERN LHC）等要求微秒级延迟的场景中，神经网络通常部署于完全展开并流水化的FPGA上。其主要瓶颈在于面积利用率，这与频繁进行的常量矩阵-向量乘法（CMVM）操作密切相关。本文提出一种基于分布式算术的高效CMVM实现算法，在FPGA上同时优化面积消耗与计算延迟。该算法在资源占用方面达到与当前先进方法相当的水平，且计算速度显著提升。所提算法已开源并集成至hls4ml库——一个用于FPGA上实时神经网络推理的免费开源工具。实验表明，对于实际的高量化神经网络，该算法可将片上资源使用减少高达三分之一，同时降低延迟，使此前无法实现的网络成为可能。
原文摘要 · Abstract (English)
Neural networks with a latency requirement on the order of microseconds, like the ones used at the CERN Large Hadron Collider, are typically deployed on FPGAs fully unrolled and pipelined. A bottleneck for the deployment of such neural networks is area utilization, which is directly related to the required constant matrix-vector multiplication (CMVM) operations. In this work, we propose an efficient algorithm for implementing CMVM operations with distributed arithmetic on FPGAs that simultaneously optimizes for area consumption and latency. The algorithm achieves resource reduction similar to state-of-the-art algorithms while being significantly faster to compute. The proposed algorithm is open-sourced and integrated into the \texttt{hls4ml} library, a free and open-source library for running real-time neural network inference on FPGAs. We show that the proposed algorithm can reduce on-chip resources by up to a third for realistic, highly quantized neural networks while simultaneously reducing latency, enabling the implementation of previously infeasible networks.
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