用深度学习预测SRAM预布局寄生电容，减少设计迭代。
Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs
- 两阶段模型：GNN分类+MLP回归，处理网表不平衡问题。
- 误差降低最多19倍，仿真速度提升最高598倍。
- 适合芯片设计工程师快速预估寄生效应。
为提升系统能效，SoC中的SRAM常需定制化设计。然而，寄生效应导致预布局与后布局仿真结果差异显著，使设计参数难收敛且需多次迭代。本文提出一种基于深度学习的两阶段模型，可准确预测预布局阶段的寄生参数。该模型结合图神经网络（GNN）分类器与多层感知机（MLP）回归器，有效处理SRAM电路中网表的类别不平衡问题。通过引入焦点损失（Focal Loss）缓解大量内部网样本的影响，并将子电路信息融入图结构以抽象原理图的层次特性。在4个真实SRAM设计上的实验表明，本方法在寄生参数预测上相比最先进模型误差最大降低19倍，仿真效率最高提升598倍。
原文摘要 · Abstract (English)
To achieve higher system energy efficiency, SRAM in SoCs is often customized. The parasitic effects cause notable discrepancies between pre-layout and post-layout circuit simulations, leading to difficulty in converging design parameters and excessive design iterations. Is it possible to well predict the parasitics based on the pre-layout circuit, so as to perform parasitic-aware pre-layout simulation? In this work, we propose a deep-learning-based 2-stage model to accurately predict these parasitics in pre-layout stages. The model combines a Graph Neural Network (GNN) classifier and Multi-Layer Perceptron (MLP) regressors, effectively managing class imbalance of the net parasitics in SRAM circuits. We also employ Focal Loss to mitigate the impact of abundant internal net samples and integrate subcircuit information into the graph to abstract the hierarchical structure of schematics. Experiments on 4 real SRAM designs show that our approach not only surpasses the state-of-the-art model in parasitic prediction by a maximum of 19X reduction of error but also significantly boosts the simulation process by up to 598X speedup.
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