用脉冲神经网络在FPGA上加速手写数字识别，低功耗实时响应。
SFATTI: Spiking FPGA Accelerator for Temporal Task-driven Inference -- A Case Study on MNIST
- 基于Spiker+框架自动生成优化的脉冲神经网络硬件
- 在MNIST数据集上实现低延迟、低功耗的边缘推理
- 适合对能效和实时性要求高的嵌入式视觉应用
硬件加速器对于实现边缘应用中图像识别的低延迟、低功耗推理至关重要。脉冲神经网络（SNNs）因其事件驱动和时间稀疏特性，特别适合在低功耗现场可编程门阵列（FPGA）上部署。本文利用开源Spiker+框架，为手写数字识别任务在MNIST数据集上生成优化的SNN加速器。Spiker+支持网络拓扑、神经元模型和量化参数的高层描述，可自动生成可部署的HDL代码。我们评估了多种配置，并分析了与边缘计算约束相关的权衡关系。
原文摘要 · Abstract (English)
Hardware accelerators are essential for achieving low-latency, energy-efficient inference in edge applications like image recognition. Spiking Neural Networks (SNNs) are particularly promising due to their event-driven and temporally sparse nature, making them well-suited for low-power Field Programmable Gate Array (FPGA)-based deployment. This paper explores using the open-source Spiker+ framework to generate optimized SNNs accelerators for handwritten digit recognition on the MNIST dataset. Spiker+ enables high-level specification of network topologies, neuron models, and quantization, automatically generating deployable HDL. We evaluate multiple configurations and analyze trade-offs relevant to edge computing constraints.
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