构建了迄今最大最高质量的Verilog代码数据集，支持大模型生成硬件代码。
VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation
- 通过数据库+代码平台+自动化校验三步构建高质量Verilog数据集
- 含20,392个样本、751MB代码，是当前最大的高质Verilog数据集
- 适合做LLM硬件生成研究的学者和工程师使用
大型语言模型（LLMs）在硬件设计自动化中日益流行，尤其体现在寄存器传输级（RTL）代码生成方面。本文分析了现有基于LLM的RTL生成文献，明确了训练与微调数据集的关键要求。通过自动化三阶段流程——基于PostgreSQL的数据库创建与管理、从OpenCores和GitHub等代码托管平台收集数据、以及数据预处理（包括语法验证、逻辑综合运行和模块元数据提取），构建了一个稳健的Verilog数据集。我们实现了可扩展高效的数据库基础设施以支持分析，并详细描述了预处理流水线，确保插入数据库前的数据质量。最终数据集包含20,392个Verilog样本，共751MB代码数据，据我们所知是目前最大且高质量的用于LLM微调的Verilog数据集。我们还评估了该数据集，讨论相关挑战，并探索其在未来基于大模型的硬件生成研究与开发中的潜在应用。
原文摘要 · Abstract (English)
Large Language Models (LLMs) are gaining popularity for hardware design automation, particularly through Register Transfer Level (RTL) code generation. In this work, we examine the current literature on RTL generation using LLMs and identify key requirements for training and fine-tuning datasets. We construct a robust Verilog dataset through an automated three-pronged process involving database (DB) creation and management with PostgreSQL, data collection from code hosting sites like OpenCores and GitHub, and data preprocessing to verify the codes' syntax, run logic synthesis, and extract relevant module metadata. We implement a scalable and efficient DB infrastructure to support analysis and detail our preprocessing pipeline to enforce high-quality data before DB insertion. The resulting dataset comprises 20,392 Verilog samples, 751 MB of Verilog code data, which is the largest high-quality Verilog dataset for LLM fine-tuning to our knowledge. We further evaluate the dataset, address associated challenges, and explore potential applications for future research and development in LLM-based hardware generation.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。