用AI自动生成硬件安全验证断言，提升效率与准确性
SVAgent: AI Agent for Hardware Security Verification Assertion
- 将复杂安全需求分解为可逐步解决的小任务链
- 生成的断言准确率和一致性显著优于现有方法
- 已在主流工程环境中验证，适合芯片安全团队使用
使用SystemVerilog断言（SVA）进行验证是检测电路设计漏洞最常用的方法之一。然而，随着集成电路设计的全球化和安全要求的持续升级，SVA开发模式暴露出重大局限：不仅开发效率低下，且难以应对现代复杂芯片中日益增长的安全漏洞。针对这一挑战，本文提出一种创新的SVA自动生成框架SVAgent。SVAgent引入需求分解机制，将原始复杂需求转化为结构化、可逐步求解的细粒度问题链。实验表明，SVAgent能有效抑制幻觉和随机回答的影响，其关键评估指标如断言准确率和一致性均显著优于现有框架。更重要的是，我们已成功将SVAgent集成至最主流的集成电路漏洞评估框架，并在真实工程设计环境中验证了其实用性和可靠性。
原文摘要 · Abstract (English)
Verification using SystemVerilog assertions (SVA) is one of the most popular methods for detecting circuit design vulnerabilities. However, with the globalization of integrated circuit design and the continuous upgrading of security requirements, the SVA development model has exposed major limitations. It is not only inefficient in development, but also unable to effectively deal with the increasing number of security vulnerabilities in modern complex integrated circuits. In response to these challenges, this paper proposes an innovative SVA automatic generation framework SVAgent. SVAgent introduces a requirement decomposition mechanism to transform the original complex requirements into a structured, gradually solvable fine-grained problem-solving chain. Experiments have shown that SVAgent can effectively suppress the influence of hallucinations and random answers, and the key evaluation indicators such as the accuracy and consistency of the SVA are significantly better than existing frameworks. More importantly, we successfully integrated SVAgent into the most mainstream integrated circuit vulnerability assessment framework and verified its practicality and reliability in a real engineering design environment.
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