用磁畴壁随机性实现高效贝叶斯神经网络,提升AI可靠性。
Spintronic Bayesian Hardware Driven by Stochastic Magnetic Domain Wall Dynamics
- 利用磁畴壁热随机性与电控各向异性实现全电调控概率计算。
- 在CIFAR-10任务中相比28nm CMOS功耗降低10^7倍,速度与面积显著优化。
- 适合对可靠性要求高的安全关键场景,如自动驾驶、医疗诊断。
随着人工智能(AI)向多样化应用发展,模型可靠性日益重要。传统神经网络虽具强大预测能力,但输出确定且无内在不确定性估计,限制其在安全关键领域的应用。概率神经网络(PNN)引入随机性,可实现内在不确定性量化,但传统CMOS架构以确定性运行为基础,主动抑制固有随机性,导致概率计算带来巨大算力开销。为此,我们提出磁概率计算(MPC)平台——一种基于自旋电子学磁畴壁(DW)动力学的低功耗、可扩展硬件加速器,通过物理随机性实现不确定性感知计算。该平台融合热驱动畴壁随机性、电压控制磁各向异性(VCMA)与隧穿磁阻(TMR)机制,在器件级实现全电调控的概率功能。作为典型验证,我们在CIFAR-10分类任务上实现了贝叶斯神经网络(BNN)推理,相较标准28nm CMOS实现整体性能指标提升七数量级,显著改善面积效率、能耗与速度。结果表明,MPC平台有望推动可靠可信的物理级AI系统发展。
原文摘要 · Abstract (English)
As artificial intelligence (AI) advances into diverse applications, ensuring reliability of AI models is increasingly critical. Conventional neural networks offer strong predictive capabilities but produce deterministic outputs without inherent uncertainty estimation, limiting their reliability in safety-critical domains. Probabilistic neural networks (PNNs), which introduce randomness, have emerged as a powerful approach for enabling intrinsic uncertainty quantification. However, traditional CMOS architectures are inherently designed for deterministic operation and actively suppress intrinsic randomness. This poses a fundamental challenge for implementing PNNs, as probabilistic processing introduces significant computational overhead. To address this challenge, we introduce a Magnetic Probabilistic Computing (MPC) platform-an energy-efficient, scalable hardware accelerator that leverages intrinsic magnetic stochasticity for uncertainty-aware computing. This physics-driven strategy utilizes spintronic systems based on magnetic domain walls (DWs) and their dynamics to establish a new paradigm of physical probabilistic computing for AI. The MPC platform integrates three key mechanisms: thermally induced DW stochasticity, voltage controlled magnetic anisotropy (VCMA), and tunneling magnetoresistance (TMR), enabling fully electrical and tunable probabilistic functionality at the device level. As a representative demonstration, we implement a Bayesian Neural Network (BNN) inference structure and validate its functionality on CIFAR-10 classification tasks. Compared to standard 28nm CMOS implementations, our approach achieves a seven orders of magnitude improvement in the overall figure of merit, with substantial gains in area efficiency, energy consumption, and speed. These results underscore the MPC platform's potential to enable reliable and trustworthy physical AI systems.
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