通过部分流程轨迹分析，定位晶圆缺陷的上游根源
Wafer Defect Root Cause Analysis with Partial Trajectory Regression
- 基于部分流程轨迹对比，计算各工序的缺陷贡献度
- 在纽约创智厂真实数据上验证，准确识别高缺陷率源头工序
- 适合半导体制造中的缺陷溯源与工艺优化团队
由于工艺流程的组合特性及重加工、随机等待时间等因素导致的流程路径变异，识别造成晶圆缺陷的上游工序极具挑战。本文提出一种名为部分轨迹回归（Partial Trajectory Regression, PTR）的新框架，专门应对传统向量回归模型在处理长度可变、异构物理工序流程时的局限性。通过新设计的表示学习方法proc2vec和route2vec，该框架基于两个反事实结果的比较，为特定晶圆上检测到的高缺陷密度计算各工序的归因得分。我们在纽约创智厂（NY CREATES fab）的真实晶圆历史数据上验证了该框架的有效性。
原文摘要 · Abstract (English)
Identifying upstream processes responsible for wafer defects is challenging due to the combinatorial nature of process flows and the inherent variability in processing routes, which arises from factors such as rework operations and random process waiting times. This paper presents a novel framework for wafer defect root cause analysis, called Partial Trajectory Regression (PTR). The proposed framework is carefully designed to address the limitations of conventional vector-based regression models, particularly in handling variable-length processing routes that span a large number of heterogeneous physical processes. To compute the attribution score of each process given a detected high defect density on a specific wafer, we propose a new algorithm that compares two counterfactual outcomes derived from partial process trajectories. This is enabled by new representation learning methods, proc2vec and route2vec. We demonstrate the effectiveness of the proposed framework using real wafer history data from the NY CREATES fab in Albany.
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