解决大模型生成硬件代码的错误根源，提升准确率至98.1%。
Understanding and Mitigating Errors of LLM-Generated RTL Code
- 用检索增强生成补足领域知识，纠正编程缺陷
- 在VerilogEval上达98.1%准确率，显著优于基线
- 适合芯片设计自动化研究者与工程实践者参考
尽管基于大语言模型（LLM）的寄存器传输级（RTL）代码生成已取得一定进展，但其错误根源仍不清晰。我们开展全面的错误分析，发现多数失败并非源于推理能力不足，而是缺乏RTL编程知识、电路理解不充分、规格说明模糊或对多模态输入误解所致。为此，我们提出针对性修正方法：利用上下文学习构建检索增强生成（RAG）知识库以补充领域专长；通过设计描述规则与规则检查来明确输入；借助外部工具将多模态数据转换为大模型兼容格式；并引入迭代仿真-调试循环处理残余错误。将这些技术整合进基于大模型的框架后，在VerilogEval基准测试中使用DeepSeek-v3.2-Speciale达到98.1%准确率，验证了该方法的有效性。
原文摘要 · Abstract (English)
Despite limited success in large language model (LLM)-based register-transfer-level (RTL) code generation, the root causes of errors remain poorly understood. To address this, we conduct a comprehensive error analysis, finding that most failures arise not from deficient reasoning, but from a lack of RTL programming knowledge, insufficient circuit understanding, ambiguous specifications, or misinterpreted multimodal inputs. Leveraging in-context learning, we propose targeted correction techniques: a retrieval-augmented generation (RAG) knowledge base to supply domain expertise; design description rules with rule-checking to clarify inputs; external tools to convert multimodal data into LLM-compatible formats; and an iterative simulation-debugging loop for remaining errors. Integrating these into an LLM-based framework yields significant improvement, achieving 98.1% accuracy on the VerilogEval benchmark with DeepSeek-v3.2-Speciale, demonstrating the effectiveness of our approach.
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