将可微逻辑门引入循环网络，实现序列建模新方法
Recurrent Deep Differentiable Logic Gate Networks
- 用可微逻辑门构建循环神经网络，结合布尔运算与递归结构
- 在英德翻译任务上达到5.00 BLEU，接近GRU性能
- 为硬件加速和递归网络设计提供新思路，适合关注高效推理的研究者
尽管可微逻辑门在前馈网络中展现出潜力，但在序列建模中的应用仍属空白。本文首次提出循环深度可微逻辑门网络（RDDLGN），将布尔运算与循环架构结合，用于序列到序列学习。在WMT'14英德翻译任务上，RDDLGN训练阶段取得5.00 BLEU和30.9%准确率，逼近GRU的5.41 BLEU表现，并在推理时保持4.39 BLEU的平滑退化性能。该工作证实了基于逻辑的循环神经计算可行性，为FPGA加速及其它递归网络架构研究开辟新方向。
原文摘要 · Abstract (English)
While differentiable logic gates have shown promise in feedforward networks, their application to sequential modeling remains unexplored. This paper presents the first implementation of Recurrent Deep Differentiable Logic Gate Networks (RDDLGN), combining Boolean operations with recurrent architectures for sequence-to-sequence learning. Evaluated on WMT'14 English-German translation, RDDLGN achieves 5.00 BLEU and 30.9\% accuracy during training, approaching GRU performance (5.41 BLEU) and graceful degradation (4.39 BLEU) during inference. This work establishes recurrent logic-based neural computation as viable, opening research directions for FPGA acceleration in sequential modeling and other recursive network architectures.
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