用分类器提前剔除无效逻辑优化操作，提速近4倍。
ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
- 用分类器预判并剔除98%的无效优化路径
- 在真实电路数据上平均加速3.9倍，优于当前最优工具
- 适合需要高效逻辑综合的芯片设计团队
在电子设计自动化中，逻辑优化算子对减少门电路数量至关重要，但计算成本高昂。传统重构算子对每个节点迭代生成切割，平均失败率达98%。此前研究通过并行化降低开销，而本文提出利用分类器预先剪枝无效切割，避免无意义重综合。在EPFL基准套件及10个大型工业设计上的实验表明，该方法相较当前最先进的ABC实现，平均提速3.9倍。
原文摘要 · Abstract (English)
In electronic design automation, logic optimization operators play a crucial role in minimizing the gate count of logic circuits. However, their computation demands are high. Operators such as refactor conventionally form iterative cuts for each node, striving for a more compact representation - a task which often fails 98% on average. Prior research has sought to mitigate computational cost through parallelization. In contrast, our approach leverages a classifier to prune unsuccessful cuts preemptively, thus eliminating unnecessary resynthesis operations. Experiments on the refactor operator using the EPFL benchmark suite and 10 large industrial designs demonstrate that this technique can speedup logic optimization by 3.9x on average compared with the state-of-the-art ABC implementation.
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