用联邦学习让芯片设计大模型在不共享数据下提升性能
FedChip: Federated LLM for Artificial Intelligence Accelerator Chip Design
- 通过联邦微调让多方协作训练专用芯片设计大模型
- 相比顶尖大模型，设计质量提升超77%
- 适合芯片设计团队、AI硬件开发者使用
AI硬件设计正快速推进，设计自动化有望加速流程、提升效率并扩大用户范围。大型语言模型（LLMs）在自动化设计流程中展现出潜力，但其应用受限于数据隐私问题及领域专用训练数据的缺乏。为此，我们提出FedChip，一种用于芯片设计的联邦微调方法，使多个芯片设计方可在保护专有数据的前提下，协同优化共享的专用大模型。各方在本地私有数据上训练模型，并共同提升共享模型性能。为验证部署效果，我们构建并发布APTPU-Gen数据集，包含30,000个涵盖功耗、性能、面积（PPA）等指标的设计变体。为引导模型生成多指标均衡的设计，我们提出新评估指标Chip@k，基于预设接受标准统计评估生成设计质量。实验表明，FedChip相较高端大模型在设计质量上提升超过77%，同时保障数据隐私。
原文摘要 · Abstract (English)
AI hardware design is advancing rapidly, driven by the promise of design automation to make chip development faster, more efficient, and more accessible to a wide range of users. Amongst automation tools, Large Language Models (LLMs) offer a promising solution by automating and streamlining parts of the design process. However, their potential is hindered by data privacy concerns and the lack of domain-specific training. To address this, we introduce FedChip, a Federated fine-tuning approach that enables multiple Chip design parties to collaboratively enhance a shared LLM dedicated for automated hardware design generation while protecting proprietary data. FedChip enables parties to train the model on proprietary local data and improve the shared LLM's performance. To exemplify FedChip's deployment, we create and release APTPU-Gen, a dataset of 30k design variations spanning various performance metric values such as power, performance, and area (PPA). To encourage the LLM to generate designs that achieve a balance across multiple quality metrics, we propose a new design evaluation metric, Chip@k, which statistically evaluates the quality of generated designs against predefined acceptance criteria. Experimental results show that FedChip improves design quality by more than 77% over high-end LLMs while maintaining data privacy
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