用二次激活函数提升隐式表示效率，硬件开销降97%仍保画质领先
QuadINR: Hardware-Efficient Implicit Neural Representations Through Quadratic Activation
- 采用分段二次激活函数，增强高频信号表达能力
- 相比基线，峰值信噪比最高提升2.06dB，功耗仅6.14mW
- 适用于资源受限场景的图像视频压缩与加速推理
隐式神经表示（INRs）通过激活函数（AFs）连续编码离散信号并缓解谱偏差问题。以往方法依赖复杂激活函数，常导致显著硬件开销。本文提出QuadINR，采用分段二次激活函数，在大幅降低硬件消耗的同时实现更优性能。该函数在傅里叶级数中包含丰富的谐波成分，经神经切空间核（NTK）分析验证可有效提升高频信号表达能力。我们构建统一的N阶段流水线框架，支持各类激活函数在INRs中的高效硬件实现。在VCU128 FPGA平台和28nm ASIC工艺下完成实现。图像与视频实验表明，相比现有工作，QuadINR最高提升2.06dB PSNR，面积仅为1914μm²，动态功耗6.14mW，资源与功耗减少达97%，延迟降低最多93%。
原文摘要 · Abstract (English)
Implicit Neural Representations (INRs) encode discrete signals continuously while addressing spectral bias through activation functions (AFs). Previous approaches mitigate this bias by employing complex AFs, which often incur significant hardware overhead. To tackle this challenge, we introduce QuadINR, a hardware-efficient INR that utilizes piecewise quadratic AFs to achieve superior performance with dramatic reductions in hardware consumption. The quadratic functions encompass rich harmonic content in their Fourier series, delivering enhanced expressivity for high-frequency signals, as verified through Neural Tangent Kernel (NTK) analysis. We develop a unified $N$-stage pipeline framework that facilitates efficient hardware implementation of various AFs in INRs. We demonstrate FPGA implementations on the VCU128 platform and an ASIC implementation in a 28nm process. Experiments across images and videos show that QuadINR achieves up to 2.06dB PSNR improvement over prior work, with an area of only 1914$μ$m$^2$ and a dynamic power of 6.14mW, reducing resource and power consumption by up to 97\% and improving latency by up to 93\% vs existing baselines.
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