用FPGA实现实时去噪，降低显微与光谱成像延迟。
Scalable FPGA Framework for Real-Time Denoising in High-Throughput Imaging: A DRAM-Optimized Pipeline using High-Level Synthesis
- 通过高阶综合优化内存访问，实现流式图像直接处理
- 去噪后数据量减少，满足高速成像的实时需求
- 适合对延迟敏感的光谱/显微成像场景
高通量成像流程（如并行快速光谱映射，PRISM）产生的数据速率超出传统实时处理能力。本文提出一种基于可扩展FPGA的预处理流水线，采用高层次综合（HLS）实现，并针对基于DRAM的缓冲进行优化。该架构在流式图像数据上直接执行帧间减法与平均运算，利用突发模式AXI4接口降低延迟。所生成的计算核运行时间低于帧间隔，支持内联去噪，显著减少下游CPU/GPU分析所需的数据量。在符合PRISM规模采集条件下的验证表明，该模块化FPGA框架为光谱学和显微成像中的低延迟工作流提供了实用解决方案。
原文摘要 · Abstract (English)
High-throughput imaging workflows, such as Parallel Rapid Imaging with Spectroscopic Mapping (PRISM), generate data at rates that exceed conventional real-time processing capabilities. We present a scalable FPGA-based preprocessing pipeline for real-time denoising, implemented via High-Level Synthesis (HLS) and optimized for DRAM-backed buffering. Our architecture performs frame subtraction and averaging directly on streamed image data, minimizing latency through burst-mode AXI4 interfaces. The resulting kernel operates below the inter-frame interval, enabling inline denoising and reducing dataset size for downstream CPU/GPU analysis. Validated under PRISM-scale acquisition, this modular FPGA framework offers a practical solution for latency-sensitive imaging workflows in spectroscopy and microscopy.
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