arXiv:2509.06239cs.AI2025-09被引 2

用强化学习修复提示词,让大模型自动生成可验证的硬件代码

Proof2Silicon: Prompt Repair for Verified Code and Hardware Generation via Reinforcement Learning

  • 通过强化学习迭代优化提示词,确保生成的Dafny代码可形式化验证
  • 在100个任务上实现最高72%的端到端硬件合成成功率
  • 适合需要安全可靠硬件设计的工程师和自动化系统开发者

大语言模型在自动代码生成方面表现卓越,但常产出无法通过形式化验证的代码,而这在硬件和高安全性领域至关重要。为突破这一瓶颈,我们此前提出PREFACE框架,基于强化学习(RL)对冻结的LLM提示词进行迭代修复,引导其生成可验证的Dafny代码,无需昂贵微调。本文提出Proof2Silicon,一个嵌入PREFACE流程的端到端合成框架,可直接从自然语言规格生成正确性构建的硬件。该框架:(1) 利用验证器驱动的强化学习代理优化提示词,保障Dafny代码正确性;(2) 通过Dafny的Python后端与PyLog自动将验证后的Dafny程序转换为可综合的高层次C代码;(3) 使用Vivado HLS生成RTL实现。在100个任务的严苛基准测试中,PREFACE的强化学习提示优化使多种LLM的Dafny验证成功率提升最高达21%。关键的是,Proof2Silicon实现了高达72%的端到端硬件合成成功率,通过Vivado HLS流程生成了可部署的RTL设计。这些结果展示了高效、可扩展且全自动的LLM驱动形式化验证硬件合成管道,成功连接自然语言规格与硅芯片实现。

原文摘要 · Abstract (English)

Large Language Models (LLMs) have demonstrated impressive capabilities in automated code generation but frequently produce code that fails formal verification, an essential requirement for hardware and safety-critical domains. To overcome this fundamental limitation, we previously proposed PREFACE, a model-agnostic framework based on reinforcement learning (RL) that iteratively repairs the prompts provided to frozen LLMs, systematically steering them toward generating formally verifiable Dafny code without costly fine-tuning. This work presents Proof2Silicon, a novel end-to-end synthesis framework that embeds the previously proposed PREFACE flow to enable the generation of correctness-by-construction hardware directly from natural language specifications. Proof2Silicon operates by: (1) leveraging PREFACE's verifier-driven RL agent to optimize prompt generation iteratively, ensuring Dafny code correctness; (2) automatically translating verified Dafny programs into synthesizable high-level C using Dafny's Python backend and PyLog; and (3) employing Vivado HLS to produce RTL implementations. Evaluated rigorously on a challenging 100-task benchmark, PREFACE's RL-guided prompt optimization consistently improved Dafny verification success rates across diverse LLMs by up to 21%. Crucially, Proof2Silicon achieved an end-to-end hardware synthesis success rate of up to 72%, generating RTL designs through Vivado HLS synthesis flows. These results demonstrate a robust, scalable, and automated pipeline for LLM-driven, formally verified hardware synthesis, bridging natural-language specification and silicon realization.

硬件生成形式验证强化学习自然语言

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