用图神经网络快速预测电路隐性故障，提升芯片安全检测效率。
A Spatio-Temporal Graph Neural Networks Approach for Predicting Silent Data Corruption inducing Circuit-Level Faults
- 将电路建模为时空图，通过专用编码器高效预测多周期故障概率。
- 在ISCAS-89上实现10倍以上仿真加速，5周期预测平均误差仅0.024。
- 适用于SoC级测试策略优化，适合EDA工具链集成与风险评估。
由零时刻缺陷和老化引起的隐性数据错误会损害安全关键系统。传统功能测试虽可检测相关故障，但仿真成本高昂。本文提出一种统一的时空图卷积网络（ST-GCN），用于快速、准确地预测大规模时序电路中长周期故障影响概率（FIP），支持量化风险评估。门级网表被建模为时空图以捕捉拓扑结构与信号时序；专用的空间与时间编码器可高效预测多周期FIP。在ISCAS-89基准测试中，该方法将仿真时间减少超过10倍，同时保持高精度（5周期预测均方误差为0.024）。框架可接受可测性度量或故障仿真特征，支持效率与精度之间的权衡。测试点选择研究显示，基于预测FIP选取观测点能更好发现长周期、难检测的故障。该方法可扩展至SoC级测试策略优化，并兼容下游电子设计自动化流程。
原文摘要 · Abstract (English)
Silent Data Errors (SDEs) from time-zero defects and aging degrade safety-critical systems. Functional testing detects SDE-related faults but is expensive to simulate. We present a unified spatio-temporal graph convolutional network (ST-GCN) for fast, accurate prediction of long-cycle fault impact probabilities (FIPs) in large sequential circuits, supporting quantitative risk assessment. Gate-level netlists are modeled as spatio-temporal graphs to capture topology and signal timing; dedicated spatial and temporal encoders predict multi-cycle FIPs efficiently. On ISCAS-89 benchmarks, the method reduces simulation time by more than 10x while maintaining high accuracy (mean absolute error 0.024 for 5-cycle predictions). The framework accepts features from testability metrics or fault simulation, allowing efficiency-accuracy trade-offs. A test-point selection study shows that choosing observation points by predicted FIPs improves detection of long-cycle, hard-to-detect faults. The approach scales to SoC-level test strategy optimization and fits downstream electronic design automation flows.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。