为一次性智能产品设计低功耗芯片,按使用时长优化碳排放。
Lifetime-Aware Design for Item-Level Intelligence at the Extreme Edge
- 基于柔性电子器件,按物品寿命动态调整芯片架构设计。
- 相比传统方法,碳足迹降低1.62倍;算法优化可再降14.5倍。
- 适合可持续传感、医疗贴片等超大规模边缘智能场景。
我们提出FlexiFlow,一种面向物品级智能(ILI)的生命周期感知设计框架,将计算直接集成于食品包装、医疗贴片等一次性产品中。该框架利用原生柔性电子技术,成本远低于硅基芯片,但仅支持千赫兹级别速度和数千门规模。核心洞察是:与传统计算部署模式不同,ILI应用的运行寿命存在1000倍差异,这在万亿级部署下彻底改变了最优架构设计决策。为此,我们建立了隐含碳足迹与运行碳足迹之间的权衡模型,依据应用寿命进行优化。框架包含:(1) FlexiBench,一套面向可持续性应用的工作负载套件,涵盖变质检测与健康监测;(2) FlexiBits,面积优化的RISC-V核心,支持1/4/8位数据路径,每工作负载执行能耗效率提升2.65至3.50倍;(3) 一种碳感知模型,根据部署特征选择最优架构。实验表明,生命周期感知微架构设计可使碳足迹降低1.62倍,算法决策可进一步降低14.5倍。通过首个采用柔性电子工艺设计工具包(PDK)的全开源流片验证,实现30.9kHz运行。FlexiFlow推动了极端边缘计算的探索,要求重新审视传统设计范式以应对新约束。
原文摘要 · Abstract (English)
We present FlexiFlow, a lifetime-aware design framework for item-level intelligence (ILI) where computation is integrated directly into disposable products like food packaging and medical patches. Our framework leverages natively flexible electronics which offer significantly lower costs than silicon but are limited to kHz speeds and several thousands of gates. Our insight is that unlike traditional computing with more uniform deployment patterns, ILI applications exhibit 1000X variation in operational lifetime, fundamentally changing optimal architectural design decisions when considering trillion-item deployment scales. To enable holistic design and optimization, we model the trade-offs between embodied carbon footprint and operational carbon footprint based on application-specific lifetimes. The framework includes: (1) FlexiBench, a workload suite targeting sustainability applications from spoilage detection to health monitoring; (2) FlexiBits, area-optimized RISC-V cores with 1/4/8-bit datapaths achieving 2.65X to 3.50X better energy efficiency per workload execution; and (3) a carbon-aware model that selects optimal architectures based on deployment characteristics. We show that lifetime-aware microarchitectural design can reduce carbon footprint by 1.62X, while algorithmic decisions can reduce carbon footprint by 14.5X. We validate our approach through the first tape-out using a PDK for flexible electronics with fully open-source tools, achieving 30.9kHz operation. FlexiFlow enables exploration of computing at the Extreme Edge where conventional design methodologies must be reevaluated to account for new constraints and considerations.
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