用强化学习协调多核预取，减少冗余提升性能
Coordinated Reinforcement Learning Prefetching Architecture for Multicore Systems
- 多核间共享预取信息，协同决策避免重复请求
- 在带宽受限场景下提升约12%指令/周期（IPC）
- 适合追求高能效的多核系统设计者参考
硬件预取对弥合CPU速度与内存访问延迟之间的差距至关重要。随着多核架构普及，传统预取器面临严峻挑战：各核心独立运行导致大量冗余预取（高达20%的预取请求为重复），引发不必要的内存总线流量和带宽浪费。此外，前沿预取器Pythia在从单核扩展到四核系统时性能下降约10%。为此，我们提出CRL-Pythia，一种专为多核系统设计的基于强化学习的协同预取架构。该方法通过跨核信息共享与协作预取决策，显著减少冗余预取请求，并加速各核心的学习收敛。实验表明，CRL-Pythia在所有测试场景中均优于单核Pythia配置，在带宽受限工作负载下实现约12%的IPC提升，同时引入适度硬件开销。敏感性分析验证了其鲁棒性与可扩展性，使其成为现代多核系统的实用高效解决方案。
原文摘要 · Abstract (English)
Hardware prefetching is critical to fill the performance gap between CPU speeds and slower memory accesses. With multicore architectures becoming commonplace, traditional prefetchers are severely challenged. Independent core operation creates significant redundancy (up to 20% of prefetch requests are duplicates), causing unnecessary memory bus traffic and wasted bandwidth. Furthermore, cutting-edge prefetchers such as Pythia suffer from about a 10% performance loss when scaling from a single-core to a four-core system. To solve these problems, we propose CRL-Pythia, a coordinated reinforcement learning based prefetcher specifically designed for multicore systems. In this work, CRL-Pythia addresses these issues by enabling cross-core sharing of information and cooperative prefetching decisions, which greatly reduces redundant prefetch requests and improves learning convergence across cores. Our experiments demonstrate that CRL-Pythia outperforms single Pythia configurations in all cases, with approximately 12% IPC (instructions per cycle) improvement for bandwidth-constrained workloads, while imposing moderate hardware overhead. Our sensitivity analyses also verify its robustness and scalability, thereby making CRL-Pythia a practical and efficient solution to contemporary multicore systems.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。