提出高效映射方法，实现低功耗神经元电路与神经网络的精确对应。
Weight Mapping Properties of a Dual Tree Single Clock Adiabatic Capacitive Neuron
- 设计新映射方法，将软件训练权重精准转为模拟电路电容值。
- 验证三类网络在电路中实现100%功能等价，提升分类准确率。
- 关注芯片面积与比较器性能，助力实际硬件部署。
双树单时钟（DTSC）绝热电容神经元（ACN）电路在全定制模拟集成电路中具备实现高能效人工神经网络（ANN）计算的潜力。然而，如何将软件训练所得的人工神经元（AN）抽象权重有效映射到物理ACN电容值上，仍缺乏充分研究。本文探讨了该映射中存在的隐含复杂性、挑战与特性，并分析其对集成电路设计在精度、设计与实现方面的影响。我们提出一种优化的从人工神经元到ACN的映射方法，可缩小芯片尺寸并提升整体分类准确率，为实际应用铺路。通过TensorFlow与Larq框架训练三种不同结构的ANN模型，将其权重映射至能量高效的DTSC ACN电容域，实现100%功能等价。最后，基于芯片版图空间与比较器决策效能等实际集成电路考量，引入新型量化评估指标，深入分析权重量化对ACN性能的影响。
原文摘要 · Abstract (English)
Dual Tree Single Clock (DTSC) Adiabatic Capacitive Neuron (ACN) circuits offer the potential for highly energy-efficient Artificial Neural Network (ANN) computation in full custom analog IC designs. The efficient mapping of Artificial Neuron (AN) abstract weights, extracted from the software-trained ANNs, onto physical ACN capacitance values has, however, yet to be fully researched. In this paper, we explore the unexpected hidden complexities, challenges and properties of the mapping, as well as, the ramifications for IC designers in terms accuracy, design and implementation. We propose an optimal, AN to ACN methodology, that promotes smaller chip sizes and improved overall classification accuracy, necessary for successful practical deployment. Using TensorFlow and Larq software frameworks, we train three different ANN networks and map their weights into the energy-efficient DTSC ACN capacitance value domain to demonstrate 100% functional equivalency. Finally, we delve into the impact of weight quantization on ACN performance using novel metrics related to practical IC considerations, such as IC floor space and comparator decision-making efficacy.
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