芯片化设计让边缘AI芯片更高效可扩展
Chiplet-Based RISC-V SoC with Modular AI Acceleration
- 采用模块化芯片组架构，支持灵活升级与优化
- 实测性能提升14.7%延迟降低，能效提高40.1%
- 适合追求高能效与可迭代的边缘AI设备开发者
在先进360 mm²制程节点下，传统单片SoC因良率低于16%而难以兼顾高性能、低功耗与低成本。本文提出一种基于芯片组的RISC-V SoC架构，通过模块化AI加速与系统级智能优化解决该问题。设计集成于30mm×30mm硅中介层，包含自适应跨芯片动态电压频率调节（DVFS）、支持流控与压缩感知的AI增强UCIe协议扩展、分布式加密安全机制及传感器驱动负载迁移。核心配置为7nm RISC-V CPU芯片、两个5nm AI加速器（各15 TOPS INT8）、16GB HBM3内存堆栈及专用电源管理控制器。在MobileNetV2、ResNet-50和实时视频处理等标准基准测试中，相较于基础芯片组方案，实现约14.7%延迟降低、17.3%吞吐提升、16.2%功耗减少。综合能效提升40.1%，每轮MobileNetV2推理仅需约3.5 mJ（860 mW，244图像/秒），且所有任务均保持亚5毫秒实时响应。结果表明，模块化芯片组可在接近单片密度的同时，实现成本效益、可扩展性与可升级性，适用于下一代边缘AI设备。
原文摘要 · Abstract (English)
Achieving high performance, energy efficiency, and cost-effectiveness while maintaining architectural flexibility is a critical challenge in the development and deployment of edge AI devices. Monolithic SoC designs struggle with this complex balance mainly due to low manufacturing yields (below 16%) at advanced 360 mm^2 process nodes. This paper presents a novel chiplet-based RISC-V SoC architecture that addresses these limitations through modular AI acceleration and intelligent system level optimization. Our proposed design integrates 4 different key innovations in a 30mm x 30mm silicon interposer: adaptive cross-chiplet Dynamic Voltage and Frequency Scaling (DVFS); AI-aware Universal Chiplet Interconnect Express (UCIe) protocol extensions featuring streaming flow control units and compression-aware transfers; distributed cryptographic security across heterogeneous chiplets; and intelligent sensor-driven load migration. The proposed architecture integrates a 7nm RISC-V CPU chiplet with dual 5nm AI accelerators (15 TOPS INT8 each), 16GB HBM3 memory stacks, and dedicated power management controllers. Experimental results across industry standard benchmarks like MobileNetV2, ResNet-50 and real-time video processing demonstrate significant performance improvements. The AI-optimized configuration achieves ~14.7% latency reduction, 17.3% throughput improvement, and 16.2% power reduction compared to previous basic chiplet implementations. These improvements collectively translate to a 40.1% efficiency gain corresponding to ~3.5 mJ per MobileNetV2 inference (860 mW/244 images/s), while maintaining sub-5ms real-time capability across all experimented workloads. These performance upgrades demonstrate that modular chiplet designs can achieve near-monolithic computational density while enabling cost efficiency, scalability and upgradeability, crucial for next-generation edge AI device applications.
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