用自动工作流生成硬件代码，省去大量人工调参和训练数据。
Automated Multi-Agent Workflows for RTL Design
- 将硬件验证反馈融入多智能体流程设计，减少依赖人工规则。
- 在少量样本下提升代码合成成功率5-7%，远低于传统方法的训练成本。
- 适合需要高效生成可靠RTL代码的芯片设计团队使用。
代理型AI工作流的兴起为计算机系统设计与优化带来了新机遇。然而，在程序综合等专业领域，由于HDL代码和专有EDA资源在线稀缺，相较于常见编程任务，常需特定任务微调、高推理成本及手工编排智能体。本文提出VeriMaAS，一种用于自动生成RTL代码的多智能体框架。核心思路是将HDL工具的正式验证反馈直接整合进工作流生成过程，从而降低基于梯度更新或冗长推理路径的成本。该方法在pass@k指标上相比微调基线提升5-7%，且仅需数百个训练样本，监督成本降低一个数量级。
原文摘要 · Abstract (English)
The rise of agentic AI workflows unlocks novel opportunities for computer systems design and optimization. However, for specialized domains such as program synthesis, the relative scarcity of HDL and proprietary EDA resources online compared to more common programming tasks introduces challenges, often necessitating task-specific fine-tuning, high inference costs, and manually-crafted agent orchestration. In this work, we present VeriMaAS, a multi-agent framework designed to automatically compose agentic workflows for RTL code generation. Our key insight is to integrate formal verification feedback from HDL tools directly into workflow generation, reducing the cost of gradient-based updates or prolonged reasoning traces. Our method improves synthesis performance by 5-7% for pass@k over fine-tuned baselines, while requiring only a few hundred training examples, representing an order-of-magnitude reduction in supervision cost.
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