用专家知识精炼代码，高效筛选可信的Verilog生成结果
The Cream Rises to the Top: Efficient Reranking Method for Verilog Code Generation
- 构建专用判别模型，从语义、测试用例、功能正确性三方面评估代码
- 推理时模拟专家思维，避免耗时的测试执行，提升效率
- 适合需要高可靠性硬件代码的工程师快速获取可信方案
大语言模型在Verilog生成中因领域知识有限而表现受限。尽管采样技术能提升pass@k指标，但硬件工程师更需要一个可靠的结果而非多个不确定的候选。为此，本文将问题建模为需求与实现间的语义对齐，并提出专用于高效Verilog代码重排序的VCD-RNK判别模型。该模型通过三个维度融合专家知识：代码语义分析、测试用例生成和功能正确性评估。推理阶段显式模拟这些分析过程，避免了现有方法中计算密集型的测试执行，显著提升效率。
原文摘要 · Abstract (English)
LLMs face significant challenges in Verilog generation due to limited domain-specific knowledge. While sampling techniques improve pass@k metrics, hardware engineers need one trustworthy solution rather than uncertain candidates. To bridge this gap, we formulate it as a semantic alignment problem between requirements and Verilog implementations, and propose VCD-RNK, a discriminator model tailored for efficient Verilog code reranking. Specifically, VCD-RNKincorporates Verilog-specific reasoning by distilling expert knowledge across three dimensions: code semantic analysis, test case generation, and functional correctness assessment. By explicitly simulating the above reasoning processes during inference, VCD-RNK effectively avoids computationally intensive test execution in existing methods.
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