用多块交叉阵列残差学习，让4位精度的模拟存算设备也能高效训练神经网络。
In-memory Training on Analog Devices with Limited Conductance States via Multi-tile Residual Learning
- 分块训练+残差修正，弥补低精度权重更新的误差
- 在4位导通状态下仍达到优于现有方法的准确率
- 适合硬件资源受限但需现场训练的边缘计算场景
模拟存内计算（AIMC）加速器利用阻性交叉阵列实现深度神经网络的内存内计算，模型参数由忆阻器件的导通状态表示。然而，有效的存内训练通常需要至少8位导通状态以匹配数字基准。实现精细状态代价高昂，且常需复杂噪声抑制技术，增加电路复杂度与能耗。实际上，许多有前景的忆阻器件如ReRAM仅提供约4位分辨率，这严重损害训练精度。为在有限状态设备上实现片上训练，本文提出一种残差学习框架，通过在多个交叉阵列块上顺序学习，补偿低精度权重更新带来的残差误差。理论分析表明，最优性差距随块数增加而缩小，并实现线性收敛速率。在标准图像分类基准上的实验表明，本方法在有限状态条件下持续优于现有最先进的模拟存内训练策略，且成本分析证实其硬件开销适中。
原文摘要 · Abstract (English)
Analog in-memory computing (AIMC) accelerators enable efficient deep neural network computation directly within memory using resistive crossbar arrays, where model parameters are represented by the conductance states of memristive devices. However, effective in-memory training typically requires at least 8-bit conductance states to match digital baselines. Realizing such fine-grained states is costly and often requires complex noise mitigation techniques that increase circuit complexity and energy consumption. In practice, many promising memristive devices such as ReRAM offer only about 4-bit resolution due to fabrication constraints, and this limited update precision substantially degrades training accuracy. To enable on-chip training with these limited-state devices, this paper proposes a \emph{residual learning} framework that sequentially learns on multiple crossbar tiles to compensate the residual errors from low-precision weight updates. Our theoretical analysis shows that the optimality gap shrinks with the number of tiles and achieves a linear convergence rate. Experiments on standard image classification benchmarks demonstrate that our method consistently outperforms state-of-the-art in-memory analog training strategies under limited-state settings, while incurring only moderate hardware overhead as confirmed by our cost analysis.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。