通过显式数据复用，提升神经渲染能效与速度。
An Energy-Efficient Edge Coprocessor for Neural Rendering with Explicit Data Reuse Strategies
- 设计四阶段调度器，利用空间局部性减少内存访问。
- 能效提升2.41倍，片上内存占用降低53.42%。
- 适合低功耗设备上的实时3D图像生成应用。
神经辐射场（NeRF）已革新3D重建与渲染，实现从稀疏视角生成逼真图像。本文提出显式数据复用神经渲染（EDR-NR）架构，通过利用射线、射线包（RPs）和采样三个阶段的空间局部性，减少外部内存访问（EMAs）和缓存缺失。EDR-NR采用四阶段调度器：基于Z-order聚类射线，射线发散时优先处理滞后射线，按空间邻近性重排RPs，并根据片上特征数据可用性无序（OoO）发出采样。同时集成四层分层射线包推进（HRM）与轴对齐包围盒（AABB），实现空间跳过（SS），减少冗余计算，提升吞吐量。此外，提出均衡的特征存储分配策略，缓解SRAM银行冲突。采用40 nm工艺制造，芯片面积10.5 mm²。相比最先进加速器，其归一化能效提升2.41倍，归一化面积效率提升1.21倍，归一化吞吐量提高1.20倍，片上SRAM消耗降低53.42%。
原文摘要 · Abstract (English)
Neural radiance fields (NeRF) have transformed 3D reconstruction and rendering, facilitating photorealistic image synthesis from sparse viewpoints. This work introduces an explicit data reuse neural rendering (EDR-NR) architecture, which reduces frequent external memory accesses (EMAs) and cache misses by exploiting the spatial locality from three phases, including rays, ray packets (RPs), and samples. The EDR-NR architecture features a four-stage scheduler that clusters rays on the basis of Z-order, prioritize lagging rays when ray divergence happens, reorders RPs based on spatial proximity, and issues samples out-of-orderly (OoO) according to the availability of on-chip feature data. In addition, a four-tier hierarchical RP marching (HRM) technique is integrated with an axis-aligned bounding box (AABB) to facilitate spatial skipping (SS), reducing redundant computations and improving throughput. Moreover, a balanced allocation strategy for feature storage is proposed to mitigate SRAM bank conflicts. Fabricated using a 40 nm process with a die area of 10.5 mmX, the EDR-NR chip demonstrates a 2.41X enhancement in normalized energy efficiency, a 1.21X improvement in normalized area efficiency, a 1.20X increase in normalized throughput, and a 53.42% reduction in on-chip SRAM consumption compared to state-of-the-art accelerators.
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