用中间层提升大模型生成硬件代码的准确性，解决语义鸿沟问题。
Faver: Boosting LLM-based RTL Generation with Function Abstracted Verifiable Middleware
- 设计可验证的抽象中间层，分离电路细节与功能逻辑。
- 在实验中使生成准确率最高提升14%。
- 适合芯片设计自动化和大模型生成硬件代码的研究者。
基于大模型的RTL生成是芯片设计中自动化程度最低的环节，具有重要研究价值。然而，由于高层规格与RTL之间存在巨大语义鸿沟，且训练数据有限，现有模型生成精度不足。借鉴人类设计经验，设计与验证结合可提升准确性，但RTL测试平台数据更稀缺，不利于大模型学习。尽管大模型擅长处理Python/C等高级语言，但其与硬件代码在时空粒度上差异显著，要求模型不仅理解功能语义，还需精确匹配电路细节，难度极大。本文提出函数抽象可验证中间层（Faver），通过融合大模型友好的代码结构与规则模板，解耦电路验证细节，使大模型专注于功能实现。在SFT模型及开源模型上的实验表明，Faver可将生成准确率提升最高达14%。
原文摘要 · Abstract (English)
LLM-based RTL generation is an interesting research direction, as it holds the potential to liberate the least automated stage in the current chip design. However, due to the substantial semantic gap between high-level specifications and RTL, coupled with limited training data, existing models struggle with generation accuracy. Drawing on human experience, design with verification helps improving accuracy. However, as the RTL testbench data are even more scarce, it is not friendly for LLMs. Although LLMs excel at higher-level languages like Python/C, they have a huge semantic gap from RTL. When implementing the same functionality, Python/C code and hardware code differ significantly in the spatiotemporal granularity, requiring the LLM not only to consider high-level functional semantics but also to ensure the low-level details align with the circuit code. It is not an easy task. In this paper, we propose a function abstracted verifiable middleware (Faver) that streamlines RTL verification in LLM-based workflows. By mixing LLM-friendly code structures with a rule-based template, Faver decouples the details of circuit verification, allowing the LLM to focus on the functionality itself. In our experiments on the SFT model and open-source models, Faver improved the model's generation accuracy by up to 14%.
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