用强化学习让模拟芯片布局更易布线，显著提升成功率。
Advancing Routing-Awareness in Analog ICs Floorplanning
- 结合强化学习与图神经网络，生成更易布线的布局方案。
- 布线成功率提升73.4%，线长减少40.6%，空隙减少13.8%。
- 适合需要高布线成功率的模拟IC设计工程师使用。
与数字集成电路布局相比，模拟集成电路布局采用机器学习方法受限于电学约束和问题特异性要求，以及布局与布线步骤间的强耦合。本文针对布局工程师对即用型布线感知布局方案的需求，提出一种基于强化学习与关系图卷积神经网络的自动化布局引擎，旨在生成更具可布线性的版图。通过提高网格分辨率、精确集成引脚信息，并引入动态布线资源估计算法，有效平衡了布线效率与面积开销，最终满足工业标准。在仿真环境中评估时，相较于现有基于学习的最先进方法，本方法实现死区减少13.8%、线长降低40.6%、布线成功率提升73.4%。
原文摘要 · Abstract (English)
The adoption of machine learning-based techniques for analog integrated circuit layout, unlike its digital counterpart, has been limited by the stringent requirements imposed by electric and problem-specific constraints, along with the interdependence of floorplanning and routing steps. In this work, we address a prevalent concern among layout engineers regarding the need for readily available routing-aware floorplanning solutions. To this extent, we develop an automatic floorplanning engine based on reinforcement learning and relational graph convolutional neural network specifically tailored to condition the floorplan generation towards more routable outcomes. A combination of increased grid resolution and precise pin information integration, along with a dynamic routing resource estimation technique, allows balancing routing and area efficiency, eventually meeting industrial standards. When analyzing the place and route effectiveness in a simulated environment, the proposed approach achieves a 13.8% reduction in dead space, a 40.6% reduction in wirelength and a 73.4% increase in routing success when compared to past learning-based state-of-the-art techniques.
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