用结构图增强大模型生成硬件代码的准确率
VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts
- 从代码中提取结构图嵌入，生成带结构信息的软提示
- 在两个基准测试中均达到领先或最优正确率
- 适合需要高可靠性硬件代码生成的研究者和工程师
大语言模型（LLMs）在从自然语言生成Verilog代码方面表现出强大能力。然而，Verilog代码本身蕴含硬件电路的结构信息。如何有效利用这些结构信息以提升生成代码的功能和语法正确性仍是重大挑战。为此，我们提出VeriGRAG框架：使用图神经网络（GNNs）从Verilog代码中提取结构图嵌入，通过多模态检索器选出与当前生成任务最相关的嵌入，并经由VeriFormer模块对齐代码模态，生成结构感知的软提示。实验表明，VeriGRAG显著提升了Verilog代码生成的正确性，在VerilogEval和RTLLM两个基准上均达到当前最优或更优表现。
原文摘要 · Abstract (English)
Large language models (LLMs) have demonstrated strong capabilities in generating Verilog code from natural language descriptions. However, Verilog code inherently encodes structural information of hardware circuits. Effectively leveraging this structural information to enhance the functional and syntactic correctness of LLM-generated Verilog code remains a significant challenge. To address this challenge, we propose VeriGRAG , a novel framework that extracts structural graph embeddings from Verilog code using graph neural networks (GNNs). A multimodal retriever then selects the graph embeddings most relevant to the given generation task, which are aligned with the code modality through the VeriFormer module to generate structure-aware soft prompts. Our experiments demonstrate that VeriGRAG substantially improves the correctness of Verilog code generation, achieving state-of-the-art or superior performance across both VerilogEval and RTLLM benchmarks.
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