用多模态大模型自动生成可编辑的模拟电路图
EEschematic: Multimodal-LLM Based AI Agent for Schematic Generation of Analog Circuit
- 结合文本、图像和符号模态，将SPICE网表转为电路图
- 六种子结构示例实现少样本布局，视觉链式思维优化布线
- 生成电路图清晰对称，适合工程师直接编辑使用
电路原理图在模拟集成电路设计中至关重要，是人类理解与验证电路功能的主要媒介。尽管近期基于大语言模型（LLM）的方法在电路拓扑生成和器件尺寸设计方面展现潜力，但多数仅依赖SPICE网表等纯文本表示，缺乏对电路设计师而言直观的视觉可读性。为此，我们提出EEschematic，一个基于多模态大语言模型（MLLM）的自动模拟电路图生成AI代理。该框架融合文本、视觉与符号模态，将SPICE网表转换为人类可编辑格式的电路图。系统采用六个模拟子结构示例进行少样本布局，并引入视觉链式思维（VCoT）策略，迭代优化元件布局与连线，提升电路图的清晰度与对称性。在典型模拟电路（包括CMOS反相器、五晶体管跨导放大器5T-OTA和望远镜式共源共栅放大器）上的实验结果表明，EEschematic生成的电路图具有高视觉质量与结构正确性。
原文摘要 · Abstract (English)
Circuit schematics play a crucial role in analog integrated circuit design, serving as the primary medium for human understanding and verification of circuit functionality. While recent large language model (LLM)-based approaches have shown promise in circuit topology generation and device sizing, most rely solely on textual representations such as SPICE netlists, which lack visual interpretability for circuit designers. To address this limitation, we propose EEschematic, an AI agent for automatic analog schematic generation based on a Multimodal Large Language Model (MLLM). EEschematic integrates textual, visual, and symbolic modalities to translate SPICE netlists into schematic diagrams represented in a human-editable format. The framework uses six analog substructure examples for few-shot placement and a Visual Chain-of-Thought (VCoT) strategy to iteratively refine placement and wiring, enhancing schematic clarity and symmetry. Experimental results on representative analog circuits, including a CMOS inverter, a five-transistor operational transconductance amplifier (5T-OTA), and a telescopic cascode amplifier, demonstrate that EEschematic produces schematics with high visual quality and structural correctness.
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