针对边缘检测设计低功耗近似乘法器，提升能效比。
Approximate Signed Multiplier with Sign-Focused Compressor for Edge Detection Applications
- 采用专注符号的压缩器处理负部分积和常数1，优化结构。
- 8位实现降低29.21%功耗延迟积，功耗降14.39%。
- 集成于卷积层可完成边缘检测，适合嵌入式视觉应用。
本文提出一种面向机器学习与信号处理中边缘检测应用的近似有符号乘法器架构，引入两种符号聚焦型压缩器：A + B + C + 1 和 A + B + C + D + 1。结合精确与近似压缩器设计，重点优化常数1及负部分积的处理效率。为提升性能，对部分积矩阵的低N-1列进行截断，并引入误差补偿机制。实验表明，所提8位近似乘法器相较现有最优方案，功耗延迟积降低29.21%，功耗降低14.39%。该乘法器被集成至定制卷积层，成功实现边缘检测，验证了其在实际应用中的有效性。
原文摘要 · Abstract (English)
This paper presents an approximate signed multiplier architecture that incorporates a sign-focused compressor, specifically designed for edge detection applications in machine learning and signal processing. The multiplier incorporates two types of sign-focused compressors: A + B + C + 1 and A + B + C + D + 1. Both exact and approximate compressor designs are utilized, with a focus on efficiently handling constant value "1" and negative partial products, which frequently appear in the partial product matrices of signed multipliers. To further enhance efficiency, the lower N - 1 columns of the partial product matrix are truncated, followed by an error compensation mechanism. Experimental results show that the proposed 8-bit approximate multiplier achieves a 29.21% reduction in power delay product (PDP) and a 14.39% reduction in power compared to the best of existing multipliers. The proposed multiplier is integrated into a custom convolution layer and performs edge detection, demonstrating its practical utility in real-world applications.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。