arXiv:2510.23156cs.LGcs.AI2025-10中稿 · 2025 IEEE Annual C…被引 2

用低功耗FPGA在家具上实现高效手势识别,无需复杂预处理。

Enabling Vibration-Based Gesture Recognition on Everyday Furniture via Energy-Efficient FPGA Implementation of 1D Convolutional Networks

  • 用原始波形替代复杂谱分析,输入大小缩小21倍。
  • 设计轻量1D-CNN模型,参数减少至216万,准确率接近传统网络。
  • 支持整数量化与自动硬件生成,单次推理能耗低于1.2毫焦。

智能家居接口需求增长推动了非侵入式传感方法的发展,如基于振动的手势识别。以往研究依赖复杂的预处理和大型神经网络,需高功耗硬件,难以实际部署。本文提出一种节能方案:在低功耗FPGA上部署紧凑型神经网络,实现实时手势识别。通过三项优化:(1)以原始波形输入替代复杂谱预处理,输入尺寸缩小21倍,精度不变;(2)设计专为嵌入式FPGA优化的轻量1D-CNN与1D-SepCNN模型,参数从3690万降至216万,保持相近准确率;(3)采用整数量化与自动化RTL生成,并引入乒乓缓冲机制,在内存受限下提升可部署性。此外,扩展硬件感知搜索框架,综合考虑准确率、延迟、能耗等约束进行模型选型。在两个滑动方向数据集上测试,使用多用户普通桌面,所提方案在AMD Spartan-7 XC7S25 FPGA上实现低延迟、低功耗推理。在PS数据划分下,6位1D-CNN达0.970平均准确率,延迟9.22毫秒;8位1D-SepCNN延迟进一步降至6.83毫秒(超CPU 53倍),准确率0.949。两者单次推理能耗均低于1.2毫焦,适合长期边缘运行。

原文摘要 · Abstract (English)

The growing demand for smart home interfaces has increased interest in non-intrusive sensing methods like vibration-based gesture recognition. While prior studies demonstrated feasibility, they often rely on complex preprocessing and large Neural Networks (NNs) requiring costly high-performance hardware, resulting in high energy usage and limited real-world deployability. This study proposes an energy-efficient solution deploying compact NNs on low-power Field-Programmable Gate Arrays (FPGAs) to enable real-time gesture recognition with competitive accuracy. We adopt a series of optimizations: (1) We replace complex spectral preprocessing with raw waveform input, eliminating complex on-board preprocessing while reducing input size by 21x without sacrificing accuracy. (2) We design two lightweight architectures (1D-CNN and 1D-SepCNN) tailored for embedded FPGAs, reducing parameters from 369 million to as few as 216 while maintaining comparable accuracy. (3) With integer-only quantization and automated RTL generation, we achieve seamless FPGA deployment. A ping-pong buffering mechanism in 1D-SepCNN further improves deployability under tight memory constraints. (4) We extend a hardware-aware search framework to support constraint-driven model configuration selection, considering accuracy, deployability, latency, and energy consumption. Evaluated on two swipe-direction datasets with multiple users and ordinary tables, our approach achieves low-latency, energy-efficient inference on the AMD Spartan-7 XC7S25 FPGA. Under the PS data splitting setting, the selected 6-bit 1D-CNN reaches 0.970 average accuracy across users with 9.22 ms latency. The chosen 8-bit 1D-SepCNN further reduces latency to 6.83 ms (over 53x CPU speedup) with slightly lower accuracy (0.949). Both consume under 1.2 mJ per inference, demonstrating suitability for long-term edge operation.

手势识别FPGA边缘计算低功耗

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